Performance and energy-per-bit modeling of interconnects for post-CMOS devices

Shaloo Rakheja, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish (US)
Title of host publicationSemiconductor Research Corporation (SCR), TECHON, Austin, Texas, September 13-14, 2010
StatePublished - 2010

Cite this

Rakheja, S., & Naeemi, A. (2010). Performance and energy-per-bit modeling of interconnects for post-CMOS devices. In Semiconductor Research Corporation (SCR), TECHON, Austin, Texas, September 13-14, 2010

Performance and energy-per-bit modeling of interconnects for post-CMOS devices. / Rakheja, Shaloo; Naeemi, Azad.

Semiconductor Research Corporation (SCR), TECHON, Austin, Texas, September 13-14, 2010. 2010.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rakheja, S & Naeemi, A 2010, Performance and energy-per-bit modeling of interconnects for post-CMOS devices. in Semiconductor Research Corporation (SCR), TECHON, Austin, Texas, September 13-14, 2010.
Rakheja S, Naeemi A. Performance and energy-per-bit modeling of interconnects for post-CMOS devices. In Semiconductor Research Corporation (SCR), TECHON, Austin, Texas, September 13-14, 2010. 2010
Rakheja, Shaloo ; Naeemi, Azad. / Performance and energy-per-bit modeling of interconnects for post-CMOS devices. Semiconductor Research Corporation (SCR), TECHON, Austin, Texas, September 13-14, 2010. 2010.
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