Performance analysis of a practical load balanced switch

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The load balanced (LB) switch proposed by C.S. Chang et al [1], [2] consists of two stages. First, a load-balancing stage spreads arriving packets equally among all linecards. Then, a forwarding stage transfers packets from the linecards to their final output destination. The load balanced switch does not need any centralized scheduler and can achieve 100% throughput under a broad class of traffic distributions. In this paper, we analyze a practical load balanced switch, called the Byte-Focal switch [3], which uses packet-by-packet scheduling to significantly improve the delay performance over switches of comparable complexity. We analyze the average delay for different stages in the Byte-Focal switch. We show that the average queueing delay is roughly linear with the switch size N and although the worst case resequencing delay is N 2, the average resequencing delay is much smaller. This means that we can reduce the required resequencing buffer size significantly.

Original languageEnglish (US)
Title of host publication2006 Workshop on High Performance Switching and Routing, HPSR 2006
Pages79-84
Number of pages6
StatePublished - Dec 1 2006
Event2006 Workshop on High Performance Switching and Routing, HPSR 2006 - Poznan, Poland
Duration: Jun 7 2006Jun 9 2006

Publication series

Name2006 Workshop on High Performance Switching and Routing, HPSR 2006

Other

Other2006 Workshop on High Performance Switching and Routing, HPSR 2006
CountryPoland
CityPoznan
Period6/7/066/9/06

    Fingerprint

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Theoretical Computer Science

Cite this

Shen, Y., Panwar, S. S., & Chao, H. J. (2006). Performance analysis of a practical load balanced switch. In 2006 Workshop on High Performance Switching and Routing, HPSR 2006 (pp. 79-84). [1709685] (2006 Workshop on High Performance Switching and Routing, HPSR 2006).