Packet delay-aware scheduling in input queued switches

Yihan Li, Shivendra Panwar, H. Jonathan Chao, Jong Ha Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Virtual Output Queuing is widely used by high-speed packet switches to overcome head-of-line blocking. This is done by means of matching algorithms. In fixed-length VOQ switches, variable-length IP packets are segmented into fixedlength cells at the inputs. When a cell is transferred to its destination output, it will stay in the reassembly buffer and wait for the other cells of the same packet before the entire packet can depart the system. The delay a packet suffers in the system includes the waiting time in the VOQ, the widely studied cell delay, and the waiting time at the output reassembly buffer, the reassembly delay often ignored in many papers. Among all existing matching algorithms, Maximum Weight Matching (MWM) has the lowest average cell delay. In this paper, we investigate the average packet delay, one of the key performance measure for an input buffered packet switch. A new class of matching algorithms, PDA-MWM, is defined and proved to be stable under all admissible traffic. Three PDA-MWM matching algorithms are studied by simulation. We show that, in order to achieve low packet delay, there is a tradeoff between the cell delay performance and the reassembly delay performance. If both of them are carefully considered, a matching scheme can greatly reduce the packet delay as compared to MWM.

Original languageEnglish (US)
Title of host publicationIEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference
DOIs
StatePublished - 2006
EventIEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference - San Francisco, CA, United States
Duration: Nov 27 2006Dec 1 2006

Other

OtherIEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference
CountryUnited States
CitySan Francisco, CA
Period11/27/0612/1/06

Fingerprint

Scheduling
Switches
Personal digital assistants

Keywords

  • Delay performance
  • Scheduling
  • Stability
  • Switching
  • Virtual Output Queueing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Li, Y., Panwar, S., Chao, H. J., & Lee, J. H. (2006). Packet delay-aware scheduling in input queued switches. In IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference [4150981] https://doi.org/10.1109/GLOCOM.2006.351

Packet delay-aware scheduling in input queued switches. / Li, Yihan; Panwar, Shivendra; Chao, H. Jonathan; Lee, Jong Ha.

IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference. 2006. 4150981.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, Y, Panwar, S, Chao, HJ & Lee, JH 2006, Packet delay-aware scheduling in input queued switches. in IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference., 4150981, IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference, San Francisco, CA, United States, 11/27/06. https://doi.org/10.1109/GLOCOM.2006.351
Li Y, Panwar S, Chao HJ, Lee JH. Packet delay-aware scheduling in input queued switches. In IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference. 2006. 4150981 https://doi.org/10.1109/GLOCOM.2006.351
Li, Yihan ; Panwar, Shivendra ; Chao, H. Jonathan ; Lee, Jong Ha. / Packet delay-aware scheduling in input queued switches. IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference. 2006.
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