Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits

Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khakifirooz, Ali Afzali-Kusha

Research output: Contribution to journalArticle

Abstract

Application of the VT-control method is studied in ultra-thin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n- and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized V T-control method is a promising way for realizing low-power SOI logic circuits. Furthermore, the scalability of this technique is verified by extending the simulations to other generations of the ITRS roadmap.

Original languageEnglish (US)
Pages (from-to)505-513
Number of pages9
JournalIntegration, the VLSI Journal
Volume38
Issue number3
DOIs
StatePublished - Jan 2005

Fingerprint

Logic circuits
Voltage control
Leakage currents
Scalability
Transistors
Networks (circuits)

Keywords

  • Double-gate SOI
  • Dynamic threshold voltage
  • Low-power

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits. / Shahrjerdi, Davood; Hekmatshoar, Bahman; Khakifirooz, Ali; Afzali-Kusha, Ali.

In: Integration, the VLSI Journal, Vol. 38, No. 3, 01.2005, p. 505-513.

Research output: Contribution to journalArticle

Shahrjerdi, Davood ; Hekmatshoar, Bahman ; Khakifirooz, Ali ; Afzali-Kusha, Ali. / Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits. In: Integration, the VLSI Journal. 2005 ; Vol. 38, No. 3. pp. 505-513.
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