Optimization of the V T-control method for low-power ultra-thin double-gate SOI logic circuits

Davood Shahrjerdi, Bahman Hekmatshoar, Ali Afzali-Kusha, Ali Khakifirooz

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Application of the V T-control method is studied in ultrathin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, V CN and V CP, are applied to the back-gates of the n-type and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized V T-control method is a promising way for realizing low-power SOI logic circuits.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publicationVLSI in the Nanometer Era
Pages236-239
Number of pages4
StatePublished - Jun 28 2004
EventProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States
Duration: Apr 26 2004Apr 28 2004

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI

Other

OtherProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
CountryUnited States
CityBoston, MA
Period4/26/044/28/04

Keywords

  • Double-Gate SOI
  • Dynamic Threshold Voltage
  • Low-Power

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Shahrjerdi, D., Hekmatshoar, B., Afzali-Kusha, A., & Khakifirooz, A. (2004). Optimization of the V T-control method for low-power ultra-thin double-gate SOI logic circuits. In Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era (pp. 236-239). (Proceedings of the ACM Great Lakes Symposium on VLSI).