Optimal VLSI circuits for sorting

Research output: Contribution to journalArticle

Abstract

This work describes a large number of constructions for sorting N integers in the range [0, M - 1], for N ≤ M ≤ N2, for the standard VLSI bit model. Among other results we obtain: (1) VLSI sorter constructions that are within a constant factor of optimal size, for all M and almost all running times T; (2) a fundamentally new merging network for sorting numbers in a bit model; and (3) new organizational approaches for optimal tuning of merging networks and the proper management of data flow.

Original languageEnglish (US)
Pages (from-to)777-809
Number of pages33
JournalJournal of the ACM
Volume35
Issue number4
DOIs
StatePublished - Oct 1988

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VLSI Circuits
VLSI circuits
Sorting
Merging
Data Flow
Tuning
Integer
Model
Range of data
Standards

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Information Systems
  • Software
  • Theoretical Computer Science

Cite this

Optimal VLSI circuits for sorting. / Cole, Richard; Siegel, Alan.

In: Journal of the ACM, Vol. 35, No. 4, 10.1988, p. 777-809.

Research output: Contribution to journalArticle

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