Opportunities and pitfalls of multi-core scaling using hardware transaction memory

Zhaoguo Wang, Hao Qian, Haibo Chen, Jinyang Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Hardware transactional memory, which holds the promise to simplify and scale up multicore synchronization, has recently become available in main stream processors in the form of Intel's restricted transactional memory (RTM). Will RTM be a panacea for multicore scaling? This paper tries to shed some light on this question by studying the performance scalability of a concurrent skip list using competing synchronization techniques, including fine-grained locking, lock-free and RTM (using both Intel's RTM emulator and a real RTM machine). Our experience suggests that RTM indeed simplifies the implementation, however, a lot of care must be taken to get good performance. Specifically, to avoid excessive aborts due to RTM capacity miss or conflicts, programmers should move memory allocation/deallocation out of RTM region, tuning fallback functions, and use compiler optimization.

Original languageEnglish (US)
Title of host publicationProceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013
DOIs
StatePublished - 2013
Event4th Asia-Pacific Workshop on Systems, APSys 2013 - Singapore, Singapore
Duration: Jul 29 2013Jul 30 2013

Other

Other4th Asia-Pacific Workshop on Systems, APSys 2013
CountrySingapore
CitySingapore
Period7/29/137/30/13

Fingerprint

Computer hardware
Data storage equipment
Synchronization
Storage allocation (computer)
Scalability
Tuning

ASJC Scopus subject areas

  • Control and Systems Engineering

Cite this

Wang, Z., Qian, H., Chen, H., & Li, J. (2013). Opportunities and pitfalls of multi-core scaling using hardware transaction memory. In Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013 [3] https://doi.org/10.1145/2500727.2500745

Opportunities and pitfalls of multi-core scaling using hardware transaction memory. / Wang, Zhaoguo; Qian, Hao; Chen, Haibo; Li, Jinyang.

Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013. 2013. 3.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, Z, Qian, H, Chen, H & Li, J 2013, Opportunities and pitfalls of multi-core scaling using hardware transaction memory. in Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013., 3, 4th Asia-Pacific Workshop on Systems, APSys 2013, Singapore, Singapore, 7/29/13. https://doi.org/10.1145/2500727.2500745
Wang Z, Qian H, Chen H, Li J. Opportunities and pitfalls of multi-core scaling using hardware transaction memory. In Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013. 2013. 3 https://doi.org/10.1145/2500727.2500745
Wang, Zhaoguo ; Qian, Hao ; Chen, Haibo ; Li, Jinyang. / Opportunities and pitfalls of multi-core scaling using hardware transaction memory. Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013. 2013.
@inproceedings{15a705937f4e4343811e180110967998,
title = "Opportunities and pitfalls of multi-core scaling using hardware transaction memory",
abstract = "Hardware transactional memory, which holds the promise to simplify and scale up multicore synchronization, has recently become available in main stream processors in the form of Intel's restricted transactional memory (RTM). Will RTM be a panacea for multicore scaling? This paper tries to shed some light on this question by studying the performance scalability of a concurrent skip list using competing synchronization techniques, including fine-grained locking, lock-free and RTM (using both Intel's RTM emulator and a real RTM machine). Our experience suggests that RTM indeed simplifies the implementation, however, a lot of care must be taken to get good performance. Specifically, to avoid excessive aborts due to RTM capacity miss or conflicts, programmers should move memory allocation/deallocation out of RTM region, tuning fallback functions, and use compiler optimization.",
author = "Zhaoguo Wang and Hao Qian and Haibo Chen and Jinyang Li",
year = "2013",
doi = "10.1145/2500727.2500745",
language = "English (US)",
isbn = "9781450323161",
booktitle = "Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013",

}

TY - GEN

T1 - Opportunities and pitfalls of multi-core scaling using hardware transaction memory

AU - Wang, Zhaoguo

AU - Qian, Hao

AU - Chen, Haibo

AU - Li, Jinyang

PY - 2013

Y1 - 2013

N2 - Hardware transactional memory, which holds the promise to simplify and scale up multicore synchronization, has recently become available in main stream processors in the form of Intel's restricted transactional memory (RTM). Will RTM be a panacea for multicore scaling? This paper tries to shed some light on this question by studying the performance scalability of a concurrent skip list using competing synchronization techniques, including fine-grained locking, lock-free and RTM (using both Intel's RTM emulator and a real RTM machine). Our experience suggests that RTM indeed simplifies the implementation, however, a lot of care must be taken to get good performance. Specifically, to avoid excessive aborts due to RTM capacity miss or conflicts, programmers should move memory allocation/deallocation out of RTM region, tuning fallback functions, and use compiler optimization.

AB - Hardware transactional memory, which holds the promise to simplify and scale up multicore synchronization, has recently become available in main stream processors in the form of Intel's restricted transactional memory (RTM). Will RTM be a panacea for multicore scaling? This paper tries to shed some light on this question by studying the performance scalability of a concurrent skip list using competing synchronization techniques, including fine-grained locking, lock-free and RTM (using both Intel's RTM emulator and a real RTM machine). Our experience suggests that RTM indeed simplifies the implementation, however, a lot of care must be taken to get good performance. Specifically, to avoid excessive aborts due to RTM capacity miss or conflicts, programmers should move memory allocation/deallocation out of RTM region, tuning fallback functions, and use compiler optimization.

UR - http://www.scopus.com/inward/record.url?scp=84883112612&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883112612&partnerID=8YFLogxK

U2 - 10.1145/2500727.2500745

DO - 10.1145/2500727.2500745

M3 - Conference contribution

SN - 9781450323161

BT - Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013

ER -