Opportunities and pitfalls of multi-core scaling using hardware transaction memory

Zhaoguo Wang, Hao Qian, Haibo Chen, Jinyang Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Hardware transactional memory, which holds the promise to simplify and scale up multicore synchronization, has recently become available in main stream processors in the form of Intel's restricted transactional memory (RTM). Will RTM be a panacea for multicore scaling? This paper tries to shed some light on this question by studying the performance scalability of a concurrent skip list using competing synchronization techniques, including fine-grained locking, lock-free and RTM (using both Intel's RTM emulator and a real RTM machine). Our experience suggests that RTM indeed simplifies the implementation, however, a lot of care must be taken to get good performance. Specifically, to avoid excessive aborts due to RTM capacity miss or conflicts, programmers should move memory allocation/deallocation out of RTM region, tuning fallback functions, and use compiler optimization.

Original languageEnglish (US)
Title of host publicationProceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013
DOIs
StatePublished - Sep 2 2013
Event4th Asia-Pacific Workshop on Systems, APSys 2013 - Singapore, Singapore
Duration: Jul 29 2013Jul 30 2013

Publication series

NameProceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013

Other

Other4th Asia-Pacific Workshop on Systems, APSys 2013
CountrySingapore
CitySingapore
Period7/29/137/30/13

    Fingerprint

ASJC Scopus subject areas

  • Control and Systems Engineering

Cite this

Wang, Z., Qian, H., Chen, H., & Li, J. (2013). Opportunities and pitfalls of multi-core scaling using hardware transaction memory. In Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013 [3] (Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013). https://doi.org/10.1145/2500727.2500745