Novel test-mode-only scan attack and countermeasure for compression-based scan architectures

Sk Subidh Ali, Samah M. Saeed, Ozgur Sinanoglu, Ramesh Karri

Research output: Contribution to journalArticle

Abstract

Scan design is a de facto design-for-testability (DfT) technique that enhances access during manufacturing test process. However, it can also be used as a back door to leak secret information from a secure chip. In existing scan attacks, the secret key of a secure chip is retrieved by using both the functional mode and the test mode of the chip. These attacks can be thwarted by applying a reset operation when there is a switch of mode. However, the mode-reset countermeasure can be thwarted by using only the test mode of a secure chip. In this paper, we perform a detailed analysis on the test-mode-only scan attack. We propose attacks on an advanced encryption standard (AES) design with a basic scan architecture as well as on an AES design with an advanced DfT infrastructure that comprises decompressors and compactors. The attack results show that indeed the secure chips are vulnerable to test-mode-only attacks. The secret key can be recovered within 1 s even in the presence of decompressors and compactors. We then propose new countermeasures to thwart these attacks. The proposed countermeasures incur minimal cost while providing high success rate.

Original languageEnglish (US)
Article number7027810
Pages (from-to)808-821
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume34
Issue number5
DOIs
StatePublished - May 1 2015

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Design for testability
Cryptography
Switches
Costs

Keywords

  • AES
  • Decompressor
  • Scan Attack
  • Scan Chain
  • Scan-based DfT
  • Security
  • Testability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Novel test-mode-only scan attack and countermeasure for compression-based scan architectures. / Ali, Sk Subidh; Saeed, Samah M.; Sinanoglu, Ozgur; Karri, Ramesh.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 5, 7027810, 01.05.2015, p. 808-821.

Research output: Contribution to journalArticle

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