Abstract
As the broadband access technologies, such as DSL, cable modem, and gigabit Ethernet, are providing affordable broadband solutions to the Internet from home and the enterprise, it is required to build next generation routers with high-speed interfaces (e.g., 10 or 40 Gb/s) and large switching capacity (e.g., multipetabit). This paper first points out the issues of building such routers, such as memory speed constraint, packet arbitration bottleneck, and interconnection complexity. It then presents several algorithms/architectures to implement IP route lookup, packet classification, and switch fabrics. Some of the functions, such as packet classification, route lookup, and traffic management, can be implemented with emerging network processors that have the advantages of providing flexibility to new applications and protocols, shortening the design cycle and time-to-market, and reducing the implementation cost by avoiding the ASIC approach. Several proposed algorithms for IP route lookup and packet classification are compared in respect to their search/update speeds and storage requirements. Different efficient arbitration schemes for output port contention resolution are presented and analyzed. The paper also surveys various switch architectures of commercial routers and switch chip sets. At the end, it outlines several challenging issues that remain to be researched for next generation routers.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1518-1558 |
| Number of pages | 41 |
| Journal | Proceedings of the IEEE |
| Volume | 90 |
| Issue number | 9 |
| DOIs | |
| State | Published - 2002 |
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Keywords
- Clos network switches
- High-performance routers
- IP route lookup
- Network processors
- Packet arbitration
- Packet classification
- Packet scheduling
- Packet switches
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Next generation routers. / Chao, H. Jonathan.
In: Proceedings of the IEEE, Vol. 90, No. 9, 2002, p. 1518-1558.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Next generation routers
AU - Chao, H. Jonathan
PY - 2002
Y1 - 2002
N2 - As the broadband access technologies, such as DSL, cable modem, and gigabit Ethernet, are providing affordable broadband solutions to the Internet from home and the enterprise, it is required to build next generation routers with high-speed interfaces (e.g., 10 or 40 Gb/s) and large switching capacity (e.g., multipetabit). This paper first points out the issues of building such routers, such as memory speed constraint, packet arbitration bottleneck, and interconnection complexity. It then presents several algorithms/architectures to implement IP route lookup, packet classification, and switch fabrics. Some of the functions, such as packet classification, route lookup, and traffic management, can be implemented with emerging network processors that have the advantages of providing flexibility to new applications and protocols, shortening the design cycle and time-to-market, and reducing the implementation cost by avoiding the ASIC approach. Several proposed algorithms for IP route lookup and packet classification are compared in respect to their search/update speeds and storage requirements. Different efficient arbitration schemes for output port contention resolution are presented and analyzed. The paper also surveys various switch architectures of commercial routers and switch chip sets. At the end, it outlines several challenging issues that remain to be researched for next generation routers.
AB - As the broadband access technologies, such as DSL, cable modem, and gigabit Ethernet, are providing affordable broadband solutions to the Internet from home and the enterprise, it is required to build next generation routers with high-speed interfaces (e.g., 10 or 40 Gb/s) and large switching capacity (e.g., multipetabit). This paper first points out the issues of building such routers, such as memory speed constraint, packet arbitration bottleneck, and interconnection complexity. It then presents several algorithms/architectures to implement IP route lookup, packet classification, and switch fabrics. Some of the functions, such as packet classification, route lookup, and traffic management, can be implemented with emerging network processors that have the advantages of providing flexibility to new applications and protocols, shortening the design cycle and time-to-market, and reducing the implementation cost by avoiding the ASIC approach. Several proposed algorithms for IP route lookup and packet classification are compared in respect to their search/update speeds and storage requirements. Different efficient arbitration schemes for output port contention resolution are presented and analyzed. The paper also surveys various switch architectures of commercial routers and switch chip sets. At the end, it outlines several challenging issues that remain to be researched for next generation routers.
KW - Clos network switches
KW - High-performance routers
KW - IP route lookup
KW - Network processors
KW - Packet arbitration
KW - Packet classification
KW - Packet scheduling
KW - Packet switches
UR - http://www.scopus.com/inward/record.url?scp=0141524334&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0141524334&partnerID=8YFLogxK
U2 - 10.1109/JPROC.2002.802001
DO - 10.1109/JPROC.2002.802001
M3 - Article
AN - SCOPUS:0141524334
VL - 90
SP - 1518
EP - 1558
JO - Proceedings of the IEEE
JF - Proceedings of the IEEE
SN - 0018-9219
IS - 9
ER -