Modeling Scan Chain Modifications for Scan-in Test Power Minimization

Ozgur Sinanoglu, Alex Orailoglu

Research output: Contribution to journalConference article

Abstract

Rapid and reliable test of SOCs necessitates upfront consideration of the test power issues. Special attention should be paid to scan-based cores as the test power problem is more severe due to excessive switching activity stemming from scan chain transitions during shift operations. We propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain through logic gate insertion between scan cells, reducing scan chain transitions. We provide a mathematical analysis that helps model the impact of scan chain modifications on test stimuli transformations. Based on this analysis, we develop algorithms for transforming a set of test vectors into power-optimal test stimuli through cost-effective scan chain modifications. Even in the highly challenging case of fully specified test vectors, more than an order of magnitude reduction in scan-in power is attained by the proposed methodology, exceeding previous power reduction levels significantly.

Original languageEnglish (US)
Pages (from-to)602-611
Number of pages10
JournalIEEE International Test Conference (TC)
StatePublished - Nov 6 2003
EventProceedings International Test Conference 2003 - Charlotte, NC, United States
Duration: Sep 30 2003Oct 2 2003

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Logic gates
Modeling
Costs
Optimal Test
Methodology
Mathematical Analysis
Insertion
Transform
Logic
Cell
Model

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Modeling Scan Chain Modifications for Scan-in Test Power Minimization. / Sinanoglu, Ozgur; Orailoglu, Alex.

In: IEEE International Test Conference (TC), 06.11.2003, p. 602-611.

Research output: Contribution to journalConference article

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