Modeling, detection, and diagnosis of faults in multilevel memristor memories

Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu

Research output: Contribution to journalArticle

Abstract

Memristors are an attractive option for use in future memory architectures but are prone to high defect densities due to the nondeterministic nature of nanoscale fabrication. Several works discuss memristor fault models and testing. However, none of them considers the memristor as a multilevel cell (MLC). The ability of memristors to function as an MLC allows for extremely dense, low-power memories. Using a memristor as an MLC introduces fault mechanisms that cannot occur in typical two-level memory cells. In this paper, we develop fault models for memristor-based MLC crossbars. The typical approach to testing a memory subsystem entails testing one memory cell at a time. However, this testing strategy is time consuming and does not scale for dense, memristor memories. We propose an efficient testing technique that exploits sneak-paths inherent in crossbar memories to test several memory cells simultaneously. In this paper, we integrate solutions for detecting and locating faults in memristors. We develop a power aware built-in self-test solution to detect these faults. We also propose a hybrid diagnosis scheme that uses a combination of sneak-path and March testing to reduce diagnosis time. The proposed schemes enable and leverage sneak-paths during fault detection and diagnosis modes, while disabling sneak-paths during normal operation. The proposed hybrid scheme reduces fault detection and diagnosis time by 24.69% and 28%, respectively, compared to traditional March tests.

Original languageEnglish (US)
Article number7017558
Pages (from-to)822-834
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume34
Issue number5
DOIs
StatePublished - May 1 2015

Fingerprint

Memristors
Data storage equipment
Testing
Fault detection
Failure analysis
Memory architecture
Built-in self test
Defect density
Fabrication

Keywords

  • Built-in tests
  • Fault diagnosis
  • Memristors
  • Multi-level memory
  • Sneak-paths

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Modeling, detection, and diagnosis of faults in multilevel memristor memories. / Kannan, Sachhidh; Karimi, Naghmeh; Karri, Ramesh; Sinanoglu, Ozgur.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 5, 7017558, 01.05.2015, p. 822-834.

Research output: Contribution to journalArticle

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