Methods of suppression or avoidance of parallel-plate power leakage from conductor-backed transmission lines

Research output: Contribution to journalArticle

Abstract

Four useful methods are presented to suppress and/or avoid parallel-plate leakage from conductor-backed printed transmission lines. These include: 1) the use of shorting-pins; 2) the use of a dielectric-guide-coupled configuration; 3) using a two-layered conductor-backing configuration; and 4) dielectric loading on top. New analyses to model the leakage suppression due to the shorting-strips and the dielectric-guide-coupled geometries are presented, with selected demonstrative results and critical discussions. It is concluded that the unwanted leakage in many printed transmission lines, that are otherwise attractive for integrated circuits and phased array applications, can be successfully avoided and/or significantly suppressed using the proposed techniques.

Original languageEnglish (US)
Pages (from-to)169-181
Number of pages13
JournalIEEE Transactions on Microwave Theory and Techniques
Volume44
Issue number2
DOIs
StatePublished - 1996

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avoidance
parallel plates
transmission lines
Electric lines
leakage
conductors
retarding
backups
phased arrays
configurations
integrated circuits
Integrated circuits
strip
Geometry
geometry

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

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abstract = "Four useful methods are presented to suppress and/or avoid parallel-plate leakage from conductor-backed printed transmission lines. These include: 1) the use of shorting-pins; 2) the use of a dielectric-guide-coupled configuration; 3) using a two-layered conductor-backing configuration; and 4) dielectric loading on top. New analyses to model the leakage suppression due to the shorting-strips and the dielectric-guide-coupled geometries are presented, with selected demonstrative results and critical discussions. It is concluded that the unwanted leakage in many printed transmission lines, that are otherwise attractive for integrated circuits and phased array applications, can be successfully avoided and/or significantly suppressed using the proposed techniques.",
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