Memristor based programmable threshold logic array

Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.

Original languageEnglish (US)
Title of host publicationProceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
Pages5-10
Number of pages6
DOIs
StatePublished - 2010
Event2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 - Anaheim, CA, United States
Duration: Jun 17 2010Jun 18 2010

Other

Other2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
CountryUnited States
CityAnaheim, CA
Period6/17/106/18/10

Fingerprint

Threshold logic
Memristors
Boolean functions
Computer aided design
Transistors

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Rajendran, J., Manem, H., Karri, R., & Rose, G. S. (2010). Memristor based programmable threshold logic array. In Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 (pp. 5-10). [5510933] https://doi.org/10.1109/NANOARCH.2010.5510933

Memristor based programmable threshold logic array. / Rajendran, Jeyavijayan; Manem, Harika; Karri, Ramesh; Rose, Garrett S.

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010. 2010. p. 5-10 5510933.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rajendran, J, Manem, H, Karri, R & Rose, GS 2010, Memristor based programmable threshold logic array. in Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010., 5510933, pp. 5-10, 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, United States, 6/17/10. https://doi.org/10.1109/NANOARCH.2010.5510933
Rajendran J, Manem H, Karri R, Rose GS. Memristor based programmable threshold logic array. In Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010. 2010. p. 5-10. 5510933 https://doi.org/10.1109/NANOARCH.2010.5510933
Rajendran, Jeyavijayan ; Manem, Harika ; Karri, Ramesh ; Rose, Garrett S. / Memristor based programmable threshold logic array. Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010. 2010. pp. 5-10
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