Mapping nested loop algorithms into multidimensional systolic arrays

Pei Zong Lee, Zvi Kedem

Research output: Contribution to journalArticle

Abstract

Consideration is given to transforming depth p-nested for loop algorithms into q-dimensional systolic VLSI arrays where 1 ≤ q ≤ p-1. Previously, there existed complete characterizations of correct transformation only for the cases where q = p-1 or q = 1. This gap is filled by giving formal necessary and sufficient conditions for correct transformation of a p-nested loop algorithm into a q-dimensional systolic array for any q, 1 ≤ q ≤ p-1. Practical methods are presented. The techniques developed are applied to the automatic design of special purpose and programmable systolic arrays. The results also contribute toward automatic compilation onto more general purpose programmable arrays. Synthesis of linear and planar systolic array implementations for a three-dimensional cube-graph algorithm and a reindexed Warshall-Floyd path-finding algorithm are used to illustrate the method.

Original languageEnglish (US)
Pages (from-to)64-76
Number of pages13
JournalIEEE Transactions on Parallel and Distributed Systems
Volume1
Issue number1
DOIs
StatePublished - Jan 1990

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Systolic arrays

ASJC Scopus subject areas

  • Computational Theory and Mathematics

Cite this

Mapping nested loop algorithms into multidimensional systolic arrays. / Lee, Pei Zong; Kedem, Zvi.

In: IEEE Transactions on Parallel and Distributed Systems, Vol. 1, No. 1, 01.1990, p. 64-76.

Research output: Contribution to journalArticle

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