Mapping nested loop algorithms into multi-dimensional systolic arrays

PeiZong Lee, Zvi Kedem

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This study is concerned with transforming depth p-nested for loop algorithms into q-D systolic VLSI arrays, where 1 ≤ q ≤ p - 1. Previously, there existed necessary and sufficient conditions only for the cases when q = p - 1 and q = 1. The authors fill in this gap by giving formal conditions for correct transformations of a p-nested loop algorithm into a q-D systolic array for any q, 1 ≤ q ≤ p - 1. The techniques developed contribute towards the automatic design of special-purpose systolic arrays and automatic compilation onto more general-purpose programmable arrays.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
Editors Anon
PublisherPubl by IEEE
Pages206-210
Number of pages5
Volume3
StatePublished - 1989
EventProceedings of the 1989 International Conference on Parallel Processing - University Park, PA, USA
Duration: Aug 8 1989Aug 12 1989

Other

OtherProceedings of the 1989 International Conference on Parallel Processing
CityUniversity Park, PA, USA
Period8/8/898/12/89

Fingerprint

Systolic arrays

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Lee, P., & Kedem, Z. (1989). Mapping nested loop algorithms into multi-dimensional systolic arrays. In Anon (Ed.), Proceedings of the International Conference on Parallel Processing (Vol. 3, pp. 206-210). Publ by IEEE.

Mapping nested loop algorithms into multi-dimensional systolic arrays. / Lee, PeiZong; Kedem, Zvi.

Proceedings of the International Conference on Parallel Processing. ed. / Anon. Vol. 3 Publ by IEEE, 1989. p. 206-210.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, P & Kedem, Z 1989, Mapping nested loop algorithms into multi-dimensional systolic arrays. in Anon (ed.), Proceedings of the International Conference on Parallel Processing. vol. 3, Publ by IEEE, pp. 206-210, Proceedings of the 1989 International Conference on Parallel Processing, University Park, PA, USA, 8/8/89.
Lee P, Kedem Z. Mapping nested loop algorithms into multi-dimensional systolic arrays. In Anon, editor, Proceedings of the International Conference on Parallel Processing. Vol. 3. Publ by IEEE. 1989. p. 206-210
Lee, PeiZong ; Kedem, Zvi. / Mapping nested loop algorithms into multi-dimensional systolic arrays. Proceedings of the International Conference on Parallel Processing. editor / Anon. Vol. 3 Publ by IEEE, 1989. pp. 206-210
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