Low cost permanent fault detection using ultra-reduced instruction set co-processors

Sundaram Ananthanarayan, Siddharth Garg, Hiren D. Patel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a new, low hardware overhead solution for permanent fault detection at the microarchitecture/instruction level. The proposed technique is based on an ultra-reduced instruction set co-processor (URISC) that, in its simplest form, executes only one Turing complete instruction - the subleq instruction. Thus, any instruction on the main core can be redundantly executed on the URISC using a sequence of subleq instructions, and the results can be compared, also on the URISC, to detect faults. A number of novel software and hardware techniques are proposed to decrease the performance overhead of online fault detection while keeping the error detection latency bounded including: (i) URISC routines and hardware support to check both control and data flow instructions; (ii) checking only a subset of instructions in the code based on a novel check window criterion; and (iii) URISC instruction set extensions. Our experimental results, based on FPGA synthesis and RTL simulations, illustrate the benefits of the proposed techniques.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2013
Pages933-938
Number of pages6
StatePublished - 2013
Event16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France
Duration: Mar 18 2013Mar 22 2013

Other

Other16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
CountryFrance
CityGrenoble
Period3/18/133/22/13

Fingerprint

Fault detection
Costs
Hardware
Error detection
Field programmable gate arrays (FPGA)
Coprocessor

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ananthanarayan, S., Garg, S., & Patel, H. D. (2013). Low cost permanent fault detection using ultra-reduced instruction set co-processors. In Proceedings - Design, Automation and Test in Europe, DATE 2013 (pp. 933-938). [6513642]

Low cost permanent fault detection using ultra-reduced instruction set co-processors. / Ananthanarayan, Sundaram; Garg, Siddharth; Patel, Hiren D.

Proceedings - Design, Automation and Test in Europe, DATE 2013. 2013. p. 933-938 6513642.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ananthanarayan, S, Garg, S & Patel, HD 2013, Low cost permanent fault detection using ultra-reduced instruction set co-processors. in Proceedings - Design, Automation and Test in Europe, DATE 2013., 6513642, pp. 933-938, 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013, Grenoble, France, 3/18/13.
Ananthanarayan S, Garg S, Patel HD. Low cost permanent fault detection using ultra-reduced instruction set co-processors. In Proceedings - Design, Automation and Test in Europe, DATE 2013. 2013. p. 933-938. 6513642
Ananthanarayan, Sundaram ; Garg, Siddharth ; Patel, Hiren D. / Low cost permanent fault detection using ultra-reduced instruction set co-processors. Proceedings - Design, Automation and Test in Europe, DATE 2013. 2013. pp. 933-938
@inproceedings{083c82c3526f4cba9947ee6bd8eee565,
title = "Low cost permanent fault detection using ultra-reduced instruction set co-processors",
abstract = "In this paper, we propose a new, low hardware overhead solution for permanent fault detection at the microarchitecture/instruction level. The proposed technique is based on an ultra-reduced instruction set co-processor (URISC) that, in its simplest form, executes only one Turing complete instruction - the subleq instruction. Thus, any instruction on the main core can be redundantly executed on the URISC using a sequence of subleq instructions, and the results can be compared, also on the URISC, to detect faults. A number of novel software and hardware techniques are proposed to decrease the performance overhead of online fault detection while keeping the error detection latency bounded including: (i) URISC routines and hardware support to check both control and data flow instructions; (ii) checking only a subset of instructions in the code based on a novel check window criterion; and (iii) URISC instruction set extensions. Our experimental results, based on FPGA synthesis and RTL simulations, illustrate the benefits of the proposed techniques.",
author = "Sundaram Ananthanarayan and Siddharth Garg and Patel, {Hiren D.}",
year = "2013",
language = "English (US)",
isbn = "9783981537000",
pages = "933--938",
booktitle = "Proceedings - Design, Automation and Test in Europe, DATE 2013",

}

TY - GEN

T1 - Low cost permanent fault detection using ultra-reduced instruction set co-processors

AU - Ananthanarayan, Sundaram

AU - Garg, Siddharth

AU - Patel, Hiren D.

PY - 2013

Y1 - 2013

N2 - In this paper, we propose a new, low hardware overhead solution for permanent fault detection at the microarchitecture/instruction level. The proposed technique is based on an ultra-reduced instruction set co-processor (URISC) that, in its simplest form, executes only one Turing complete instruction - the subleq instruction. Thus, any instruction on the main core can be redundantly executed on the URISC using a sequence of subleq instructions, and the results can be compared, also on the URISC, to detect faults. A number of novel software and hardware techniques are proposed to decrease the performance overhead of online fault detection while keeping the error detection latency bounded including: (i) URISC routines and hardware support to check both control and data flow instructions; (ii) checking only a subset of instructions in the code based on a novel check window criterion; and (iii) URISC instruction set extensions. Our experimental results, based on FPGA synthesis and RTL simulations, illustrate the benefits of the proposed techniques.

AB - In this paper, we propose a new, low hardware overhead solution for permanent fault detection at the microarchitecture/instruction level. The proposed technique is based on an ultra-reduced instruction set co-processor (URISC) that, in its simplest form, executes only one Turing complete instruction - the subleq instruction. Thus, any instruction on the main core can be redundantly executed on the URISC using a sequence of subleq instructions, and the results can be compared, also on the URISC, to detect faults. A number of novel software and hardware techniques are proposed to decrease the performance overhead of online fault detection while keeping the error detection latency bounded including: (i) URISC routines and hardware support to check both control and data flow instructions; (ii) checking only a subset of instructions in the code based on a novel check window criterion; and (iii) URISC instruction set extensions. Our experimental results, based on FPGA synthesis and RTL simulations, illustrate the benefits of the proposed techniques.

UR - http://www.scopus.com/inward/record.url?scp=84885645696&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84885645696&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84885645696

SN - 9783981537000

SP - 933

EP - 938

BT - Proceedings - Design, Automation and Test in Europe, DATE 2013

ER -