Logic level fault tolerance approaches targeting nanoelectronics PLAs

Rao Wenjing, Alex Orailoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A regular structure and capability to implement arbitrary logic functions in a two-level logic form have placed crossbar-based Programmable Logic Arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting logic tautology in two-level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost.

Original languageEnglish (US)
Title of host publicationProceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
Pages865-869
Number of pages5
DOIs
StatePublished - 2007
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: Apr 16 2007Apr 20 2007

Other

Other2007 Design, Automation and Test in Europe Conference and Exhibition
CountryFrance
CityNice Acropolis
Period4/16/074/20/07

Fingerprint

Nanoelectronics
Fault tolerance
Hardware
Costs

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Wenjing, R., Orailoglu, A., & Karri, R. (2007). Logic level fault tolerance approaches targeting nanoelectronics PLAs. In Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007 (pp. 865-869). [4211911] https://doi.org/10.1109/DATE.2007.364401

Logic level fault tolerance approaches targeting nanoelectronics PLAs. / Wenjing, Rao; Orailoglu, Alex; Karri, Ramesh.

Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. 2007. p. 865-869 4211911.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wenjing, R, Orailoglu, A & Karri, R 2007, Logic level fault tolerance approaches targeting nanoelectronics PLAs. in Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007., 4211911, pp. 865-869, 2007 Design, Automation and Test in Europe Conference and Exhibition, Nice Acropolis, France, 4/16/07. https://doi.org/10.1109/DATE.2007.364401
Wenjing R, Orailoglu A, Karri R. Logic level fault tolerance approaches targeting nanoelectronics PLAs. In Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. 2007. p. 865-869. 4211911 https://doi.org/10.1109/DATE.2007.364401
Wenjing, Rao ; Orailoglu, Alex ; Karri, Ramesh. / Logic level fault tolerance approaches targeting nanoelectronics PLAs. Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. 2007. pp. 865-869
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