Logic encryption

Jeyavijayan J V Rajendran, Siddharth Garg

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Logic encryption implements a built-in locking mechanism on integrated circuits (ICs) to prevent reverse engineering and intellectual property (IP) piracy by a malicious foundry and user, and hinder Trojan insertion by a malicious foundry. Since its introduction in 2008, a wide-variety of techniques have been proposed to identify the best places in the design to insert these locks such that (i) an incorrect key results in an incorrect design and (ii) an attacker cannot identify the secret key. Furthermore, conventional testing of chips with logic encryption may help an attacker break logic encryption techniques. In this chapter, we will explain how logic encryption can defeat different types of attacks in the IC supply chains and protocols to aid logic encryption. The security properties and metrics for logic encryption are defined based on the attacker’s capabilities. Furthermore, we will explain the different attacks and their countermeasures for logic encryption.

Original languageEnglish (US)
Title of host publicationHardware Protection through Obfuscation
PublisherSpringer International Publishing
Pages71-88
Number of pages18
ISBN (Electronic)9783319490199
ISBN (Print)9783319490182
DOIs
StatePublished - Jan 1 2017

Fingerprint

Cryptography
Foundries
Integrated circuits
Reverse engineering
Intellectual property
Supply chains
Testing

Keywords

  • Combinational locking
  • Hardware obfuscation
  • IP piracy
  • Key-guessing attacks
  • Logic locking
  • One-way random functions
  • Output-guessing attacks
  • Reverse engineering
  • Untrusted test facility

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)

Cite this

Rajendran, J. J. V., & Garg, S. (2017). Logic encryption. In Hardware Protection through Obfuscation (pp. 71-88). Springer International Publishing. https://doi.org/10.1007/978-3-319-49019-9_3

Logic encryption. / Rajendran, Jeyavijayan J V; Garg, Siddharth.

Hardware Protection through Obfuscation. Springer International Publishing, 2017. p. 71-88.

Research output: Chapter in Book/Report/Conference proceedingChapter

Rajendran, JJV & Garg, S 2017, Logic encryption. in Hardware Protection through Obfuscation. Springer International Publishing, pp. 71-88. https://doi.org/10.1007/978-3-319-49019-9_3
Rajendran JJV, Garg S. Logic encryption. In Hardware Protection through Obfuscation. Springer International Publishing. 2017. p. 71-88 https://doi.org/10.1007/978-3-319-49019-9_3
Rajendran, Jeyavijayan J V ; Garg, Siddharth. / Logic encryption. Hardware Protection through Obfuscation. Springer International Publishing, 2017. pp. 71-88
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