Locating multiprocessor TLBs at memory

Patricia J. Teller, Allan Gottlieb

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper compares the performance, in shared-memory multiprocessors, of locating translation-lookaside buffers (TLBs) at processors with that of locating TLBs at memory. Our comparison is based on trace-driven simulations of multiprocessors with log N-stage networks interconnecting N processors and N memory modules. For the systems and workloads studied, memory-based TLBs perform noticeably better than processor-based TLBs, provided that memory is organized as multiple paging arenas, i.e., multiple clusters of memory modules where the mapping of a page to a cluster is fixed. The cost of a processor-based TLB reload is at least log N because of network transit. In contrast, the cost of a memory-based TLB reload can be smaller, since network transits are not required. Furthermore, with multiple paging arenas, the number of reloads is smaller with memory-based TLBs.

Original languageEnglish (US)
Title of host publicationProceedings of the Hawaii International Conference on System Sciences
EditorsJay F. Nunamaker, Ralph H.Jr. Sprague
PublisherPubl by IEEE
Pages554-563
Number of pages10
Volume1
ISBN (Print)0818650508
StatePublished - 1994
EventProceedings of the 27th Hawaii International Conference on System Sciences (HICSS-27). Part 4 (of 5) - Wailea, HI, USA
Duration: Jan 4 1994Jan 7 1994

Other

OtherProceedings of the 27th Hawaii International Conference on System Sciences (HICSS-27). Part 4 (of 5)
CityWailea, HI, USA
Period1/4/941/7/94

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Data storage equipment
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Computer systems

ASJC Scopus subject areas

  • Software
  • Industrial and Manufacturing Engineering

Cite this

Teller, P. J., & Gottlieb, A. (1994). Locating multiprocessor TLBs at memory. In J. F. Nunamaker, & R. H. J. Sprague (Eds.), Proceedings of the Hawaii International Conference on System Sciences (Vol. 1, pp. 554-563). Publ by IEEE.

Locating multiprocessor TLBs at memory. / Teller, Patricia J.; Gottlieb, Allan.

Proceedings of the Hawaii International Conference on System Sciences. ed. / Jay F. Nunamaker; Ralph H.Jr. Sprague. Vol. 1 Publ by IEEE, 1994. p. 554-563.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Teller, PJ & Gottlieb, A 1994, Locating multiprocessor TLBs at memory. in JF Nunamaker & RHJ Sprague (eds), Proceedings of the Hawaii International Conference on System Sciences. vol. 1, Publ by IEEE, pp. 554-563, Proceedings of the 27th Hawaii International Conference on System Sciences (HICSS-27). Part 4 (of 5), Wailea, HI, USA, 1/4/94.
Teller PJ, Gottlieb A. Locating multiprocessor TLBs at memory. In Nunamaker JF, Sprague RHJ, editors, Proceedings of the Hawaii International Conference on System Sciences. Vol. 1. Publ by IEEE. 1994. p. 554-563
Teller, Patricia J. ; Gottlieb, Allan. / Locating multiprocessor TLBs at memory. Proceedings of the Hawaii International Conference on System Sciences. editor / Jay F. Nunamaker ; Ralph H.Jr. Sprague. Vol. 1 Publ by IEEE, 1994. pp. 554-563
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