Leveraging CMOS design tools for QCA designs

Kim Kyosun, Oh Younbo, Karri Ramesh, Orailoglu Alex

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a radical approach to designing nanoscale Quantum Dot Cellular Automata (QCA) designs by leveraging CMOS design tools such as those used for logic validation Based on design rules that guarantee deterministic digital behavior of QCA designs, we identified a finite set of legal arrangements for QCA cells. These cell arrangements can be composed to yield robust QCA building block gates (majority gate and inverters) and interconnect structures On one hand, such a hierarchical building blocks approach can be used to synthesize large scale, robust QCA designs. On the other hand, as shown in this paper, such a hierarchical building blocks approach can be used to check if QCA designs follow the robust design rules. If so, the implemented digital logic function can be extracted, translated into an equivalent Verilog or VHDL netlist, and validated using commercial CMOS design validation tools. Towards demonstrating the proposed approach, we designed a 2-bit QCA adder, extracted the digital logic, stored it in a common engineering database (OpenAccess) and validated the functionality using ModelSim CMOS simulator.

Original languageEnglish (US)
Title of host publication2008 International SoC Design Conference, ISOCC 2008
Volume2
DOIs
StatePublished - 2008
Event2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
Duration: Nov 24 2008Nov 25 2008

Other

Other2008 International SoC Design Conference, ISOCC 2008
CountryKorea, Republic of
CityBusan
Period11/24/0811/25/08

Fingerprint

Cellular automata
Semiconductor quantum dots
Computer hardware description languages
Adders
Simulators

Keywords

  • Digital logic extraction
  • Interoperability
  • Quantum-dot cellular automata
  • Signal integrity

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Cite this

Kyosun, K., Younbo, O., Ramesh, K., & Alex, O. (2008). Leveraging CMOS design tools for QCA designs. In 2008 International SoC Design Conference, ISOCC 2008 (Vol. 2). [4815714] https://doi.org/10.1109/SOCDC.2008.4815714

Leveraging CMOS design tools for QCA designs. / Kyosun, Kim; Younbo, Oh; Ramesh, Karri; Alex, Orailoglu.

2008 International SoC Design Conference, ISOCC 2008. Vol. 2 2008. 4815714.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kyosun, K, Younbo, O, Ramesh, K & Alex, O 2008, Leveraging CMOS design tools for QCA designs. in 2008 International SoC Design Conference, ISOCC 2008. vol. 2, 4815714, 2008 International SoC Design Conference, ISOCC 2008, Busan, Korea, Republic of, 11/24/08. https://doi.org/10.1109/SOCDC.2008.4815714
Kyosun K, Younbo O, Ramesh K, Alex O. Leveraging CMOS design tools for QCA designs. In 2008 International SoC Design Conference, ISOCC 2008. Vol. 2. 2008. 4815714 https://doi.org/10.1109/SOCDC.2008.4815714
Kyosun, Kim ; Younbo, Oh ; Ramesh, Karri ; Alex, Orailoglu. / Leveraging CMOS design tools for QCA designs. 2008 International SoC Design Conference, ISOCC 2008. Vol. 2 2008.
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