Interconnect performance and energy-per-bit for post-CMOS logic circuits

Modeling, analysis, and comparison with CMOS logic

Shaloo Rakheja, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

To overcome the energy dissipation limit facing virtually all field-effect devices including CMOS switches, there is a global search for devices using alternate state variables as the token of information. In this paper, physical models for latency and energy dissipation associated with various transport mechanisms are reviewed. Using stochastic wire length distribution models based on Rent's rule, the dependence of the average interconnect delay and energy dissipation on the number of gates in a circuit is obtained for alternative post-CMOS logic circuits. Further, it is demonstrated that the required number of repeaters increases rapidly with the circuit size if the token of information decays as it propagates (e.g. spin relaxation for electron spin). This puts an upper bound on the circuit size. For a spin relaxation length of L s=2μm, the maximum circuit size for random logic is limited to 40 gates if less than 10% of the switches are to be used as interconnect repeaters and if the signal amplitude at the driver is twice the receiver's threshold. This maximum circuit size increases to 2000 gates if the spin relaxation length is increased to 8m at the same signal amplitude.

Original languageEnglish (US)
Title of host publication2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011
DOIs
StatePublished - 2011
Event2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011 - Dresden, Germany
Duration: May 8 2011May 12 2011

Other

Other2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011
CountryGermany
CityDresden
Period5/8/115/12/11

Fingerprint

Logic circuits
Networks (circuits)
Energy dissipation
Telecommunication repeaters
Switches
Wire
Electrons

ASJC Scopus subject areas

  • Materials Chemistry
  • Metals and Alloys

Cite this

Rakheja, S., & Naeemi, A. (2011). Interconnect performance and energy-per-bit for post-CMOS logic circuits: Modeling, analysis, and comparison with CMOS logic. In 2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011 [5940267] https://doi.org/10.1109/IITC.2011.5940267

Interconnect performance and energy-per-bit for post-CMOS logic circuits : Modeling, analysis, and comparison with CMOS logic. / Rakheja, Shaloo; Naeemi, Azad.

2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011. 2011. 5940267.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rakheja, S & Naeemi, A 2011, Interconnect performance and energy-per-bit for post-CMOS logic circuits: Modeling, analysis, and comparison with CMOS logic. in 2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011., 5940267, 2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011, Dresden, Germany, 5/8/11. https://doi.org/10.1109/IITC.2011.5940267
Rakheja S, Naeemi A. Interconnect performance and energy-per-bit for post-CMOS logic circuits: Modeling, analysis, and comparison with CMOS logic. In 2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011. 2011. 5940267 https://doi.org/10.1109/IITC.2011.5940267
Rakheja, Shaloo ; Naeemi, Azad. / Interconnect performance and energy-per-bit for post-CMOS logic circuits : Modeling, analysis, and comparison with CMOS logic. 2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011. 2011.
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