Implementation of an ATM layer chip for B-ISDN applications

Cesar A. Johnston, H. Jonathan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The application and architecture of an experimental research prototype application specific integrated circuit designed to serve as a generic building block of the future broadband ISDN (B-ISDN) are described. The chip performs common asynchronous transfer mode (ATM) layer functions such as cell assembly and cell disassembly. A Media access control (MAC) protocol developed for a broadband customer premises network is also integrated in the chip. The chip operation modes are controlled through a microcontroller interface. The chip interfaces to the B-ISDN through a SONET STS-3c Framer chip. The ATM-layer chip has been designed using 1.2-μm CMOS technology with a die area of 5.4 mm × 5.4 mm and approximately 27,000 transistors.

Original languageEnglish (US)
Title of host publicationConference Record - International Conference on Communications
PublisherPubl by IEEE
Pages704-710
Number of pages7
ISBN (Print)0780300068
StatePublished - Dec 1 1991
EventInternational Conference on Communications - ICC 91 - Denver, CO, USA
Duration: Jun 23 1991Jun 26 1991

Publication series

NameConference Record - International Conference on Communications
Volume2
ISSN (Print)0536-1486

Other

OtherInternational Conference on Communications - ICC 91
CityDenver, CO, USA
Period6/23/916/26/91

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ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Johnston, C. A., & Chao, H. J. (1991). Implementation of an ATM layer chip for B-ISDN applications. In Conference Record - International Conference on Communications (pp. 704-710). (Conference Record - International Conference on Communications; Vol. 2). Publ by IEEE.