Highly-scalable 3D CLOS NOC for many-core CMPs

Aamir Zia, Sachhidh Kannan, Garrett Rose, H. Jonathan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Ab stract - In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and low-power interconnect infrastructure. In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. We compare the power consumption of 3D CNOC with a planar CNOC implementation and with 2D and 3D mesh topologies.

Original languageEnglish (US)
Title of host publicationProceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010
Pages229-232
Number of pages4
DOIs
StatePublished - 2010
Event8th IEEE International NEWCAS Conference, NEWCAS 2010 - Montreal, QC, Canada
Duration: Jun 20 2010Jun 23 2010

Other

Other8th IEEE International NEWCAS Conference, NEWCAS 2010
CountryCanada
CityMontreal, QC
Period6/20/106/23/10

Fingerprint

Electric power utilization
Topology
Network-on-chip
Processing

Keywords

  • 3D IC
  • CLOS
  • Network-on-chip
  • VLSI

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Zia, A., Kannan, S., Rose, G., & Chao, H. J. (2010). Highly-scalable 3D CLOS NOC for many-core CMPs. In Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010 (pp. 229-232). [5603776] https://doi.org/10.1109/NEWCAS.2010.5603776

Highly-scalable 3D CLOS NOC for many-core CMPs. / Zia, Aamir; Kannan, Sachhidh; Rose, Garrett; Chao, H. Jonathan.

Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010. 2010. p. 229-232 5603776.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zia, A, Kannan, S, Rose, G & Chao, HJ 2010, Highly-scalable 3D CLOS NOC for many-core CMPs. in Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010., 5603776, pp. 229-232, 8th IEEE International NEWCAS Conference, NEWCAS 2010, Montreal, QC, Canada, 6/20/10. https://doi.org/10.1109/NEWCAS.2010.5603776
Zia A, Kannan S, Rose G, Chao HJ. Highly-scalable 3D CLOS NOC for many-core CMPs. In Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010. 2010. p. 229-232. 5603776 https://doi.org/10.1109/NEWCAS.2010.5603776
Zia, Aamir ; Kannan, Sachhidh ; Rose, Garrett ; Chao, H. Jonathan. / Highly-scalable 3D CLOS NOC for many-core CMPs. Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010. 2010. pp. 229-232
@inproceedings{31e12ccaf2374909b4fade57bce7dfc5,
title = "Highly-scalable 3D CLOS NOC for many-core CMPs",
abstract = "Ab stract - In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and low-power interconnect infrastructure. In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. We compare the power consumption of 3D CNOC with a planar CNOC implementation and with 2D and 3D mesh topologies.",
keywords = "3D IC, CLOS, Network-on-chip, VLSI",
author = "Aamir Zia and Sachhidh Kannan and Garrett Rose and Chao, {H. Jonathan}",
year = "2010",
doi = "10.1109/NEWCAS.2010.5603776",
language = "English (US)",
isbn = "9781424468058",
pages = "229--232",
booktitle = "Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010",

}

TY - GEN

T1 - Highly-scalable 3D CLOS NOC for many-core CMPs

AU - Zia, Aamir

AU - Kannan, Sachhidh

AU - Rose, Garrett

AU - Chao, H. Jonathan

PY - 2010

Y1 - 2010

N2 - Ab stract - In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and low-power interconnect infrastructure. In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. We compare the power consumption of 3D CNOC with a planar CNOC implementation and with 2D and 3D mesh topologies.

AB - Ab stract - In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and low-power interconnect infrastructure. In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. We compare the power consumption of 3D CNOC with a planar CNOC implementation and with 2D and 3D mesh topologies.

KW - 3D IC

KW - CLOS

KW - Network-on-chip

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=78349301604&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78349301604&partnerID=8YFLogxK

U2 - 10.1109/NEWCAS.2010.5603776

DO - 10.1109/NEWCAS.2010.5603776

M3 - Conference contribution

SN - 9781424468058

SP - 229

EP - 232

BT - Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010

ER -