High-level synthesis of fault-tolerant ASICs

Ramesh Karri, Alex Orailoǧlu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Advances in VLSI technology are making it feasible to integrate millions of transistors on a single chip. Such high levels of integration are leading to single-chip systems and on-chip fault-tolerance. Whereas methodologies for designing fault-tolerant systems have been well understood, software mechanisms for the automatic synthesis of fault-tolerant application specific ICs (ASICs) remain relatively unexplored. In this paper, we develop methodologies for the high-level synthesis of fault-tolerant ASICs that maximize performance in the presence of fault-tolerance and cost constraints. The faulttolerance constraints supported include number of faults per module (fault-masking constraint) and chip reliability (reliability constraint). Our experience with the system shows that (a) it is feasible to automate design for fault-tolerance, and (b) controlled interplay between cost, performance, and fault-tolerance, during high-level synthesis, helps synthesize high quality and costeffective fault-tolerant ASICs.

Original languageEnglish (US)
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages419-422
Number of pages4
ISBN (Electronic)0780305930
DOIs
StatePublished - Jan 1 1992
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: May 10 1992May 13 1992

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume1
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period5/10/925/13/92

Fingerprint

Fault tolerance
Costs
Transistors
High level synthesis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Karri, R., & Orailoǧlu, A. (1992). High-level synthesis of fault-tolerant ASICs. In 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 (pp. 419-422). [229924] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.1992.229924

High-level synthesis of fault-tolerant ASICs. / Karri, Ramesh; Orailoǧlu, Alex.

1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 419-422 229924 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Karri, R & Orailoǧlu, A 1992, High-level synthesis of fault-tolerant ASICs. in 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992., 229924, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 419-422, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992, San Diego, United States, 5/10/92. https://doi.org/10.1109/ISCAS.1992.229924
Karri R, Orailoǧlu A. High-level synthesis of fault-tolerant ASICs. In 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 419-422. 229924. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.1992.229924
Karri, Ramesh ; Orailoǧlu, Alex. / High-level synthesis of fault-tolerant ASICs. 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. pp. 419-422 (Proceedings - IEEE International Symposium on Circuits and Systems).
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