High-k dielectrics for Ge, III-V and graphene MOSFETs

S. Banerjee, E. Tutuc, S. Kim, T. Akyol, M. Jamil, Davood Shahrjerdi, J. Donnelly, L. Colombo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

It is well known that the existence of a high quality oxide on Si has been key to the success of Si metal oxide semiconductor field effect transistors (MOSFETs). Scaling of Si CMOS logic devices to the next level has led to a flurry of activity in enhanced channel mobility materials such as III-V, Ge, and graphene. Since these materials lack a high-quality native oxide, integrating high-k gate dielectrics is necessary. Atomic layer deposition (ALD) offers precise control over the uniformity and thickness of the deposited high-k films through as well as reduction of native oxides by appropriate chemistry. Nevertheless, integrating ALD high-k on Ge, graphene and III-V materials necessitates the use of an effective chemical surface treatment protocol. This is to alter the surface properties in order to ensure full surface coverage, while preventing the re-growth of native oxides during the ex-situ sample transfer into the ALD reactor.

Original languageEnglish (US)
Title of host publicationECS Transactions - Physics and Technology of High-k Gate Dielectrics 7
Pages285-299
Number of pages15
Volume25
Edition6
DOIs
StatePublished - 2009
Event7th International Symposium on High Dielectric Constant Materials and Gate Stacks - 216th Meeting of the Electrochemical Society - Vienna, Austria
Duration: Oct 5 2009Oct 7 2009

Other

Other7th International Symposium on High Dielectric Constant Materials and Gate Stacks - 216th Meeting of the Electrochemical Society
CountryAustria
CityVienna
Period10/5/0910/7/09

Fingerprint

MOSFET devices
Graphene
Atomic layer deposition
Oxides
Logic devices
Gate dielectrics
Surface properties
Surface treatment
High-k dielectric

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Banerjee, S., Tutuc, E., Kim, S., Akyol, T., Jamil, M., Shahrjerdi, D., ... Colombo, L. (2009). High-k dielectrics for Ge, III-V and graphene MOSFETs. In ECS Transactions - Physics and Technology of High-k Gate Dielectrics 7 (6 ed., Vol. 25, pp. 285-299) https://doi.org/10.1149/1.3206627

High-k dielectrics for Ge, III-V and graphene MOSFETs. / Banerjee, S.; Tutuc, E.; Kim, S.; Akyol, T.; Jamil, M.; Shahrjerdi, Davood; Donnelly, J.; Colombo, L.

ECS Transactions - Physics and Technology of High-k Gate Dielectrics 7. Vol. 25 6. ed. 2009. p. 285-299.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Banerjee, S, Tutuc, E, Kim, S, Akyol, T, Jamil, M, Shahrjerdi, D, Donnelly, J & Colombo, L 2009, High-k dielectrics for Ge, III-V and graphene MOSFETs. in ECS Transactions - Physics and Technology of High-k Gate Dielectrics 7. 6 edn, vol. 25, pp. 285-299, 7th International Symposium on High Dielectric Constant Materials and Gate Stacks - 216th Meeting of the Electrochemical Society, Vienna, Austria, 10/5/09. https://doi.org/10.1149/1.3206627
Banerjee S, Tutuc E, Kim S, Akyol T, Jamil M, Shahrjerdi D et al. High-k dielectrics for Ge, III-V and graphene MOSFETs. In ECS Transactions - Physics and Technology of High-k Gate Dielectrics 7. 6 ed. Vol. 25. 2009. p. 285-299 https://doi.org/10.1149/1.3206627
Banerjee, S. ; Tutuc, E. ; Kim, S. ; Akyol, T. ; Jamil, M. ; Shahrjerdi, Davood ; Donnelly, J. ; Colombo, L. / High-k dielectrics for Ge, III-V and graphene MOSFETs. ECS Transactions - Physics and Technology of High-k Gate Dielectrics 7. Vol. 25 6. ed. 2009. pp. 285-299
@inproceedings{2b688e3d5bab4563a90dfa9e27dd24f2,
title = "High-k dielectrics for Ge, III-V and graphene MOSFETs",
abstract = "It is well known that the existence of a high quality oxide on Si has been key to the success of Si metal oxide semiconductor field effect transistors (MOSFETs). Scaling of Si CMOS logic devices to the next level has led to a flurry of activity in enhanced channel mobility materials such as III-V, Ge, and graphene. Since these materials lack a high-quality native oxide, integrating high-k gate dielectrics is necessary. Atomic layer deposition (ALD) offers precise control over the uniformity and thickness of the deposited high-k films through as well as reduction of native oxides by appropriate chemistry. Nevertheless, integrating ALD high-k on Ge, graphene and III-V materials necessitates the use of an effective chemical surface treatment protocol. This is to alter the surface properties in order to ensure full surface coverage, while preventing the re-growth of native oxides during the ex-situ sample transfer into the ALD reactor.",
author = "S. Banerjee and E. Tutuc and S. Kim and T. Akyol and M. Jamil and Davood Shahrjerdi and J. Donnelly and L. Colombo",
year = "2009",
doi = "10.1149/1.3206627",
language = "English (US)",
isbn = "9781566777438",
volume = "25",
pages = "285--299",
booktitle = "ECS Transactions - Physics and Technology of High-k Gate Dielectrics 7",
edition = "6",

}

TY - GEN

T1 - High-k dielectrics for Ge, III-V and graphene MOSFETs

AU - Banerjee, S.

AU - Tutuc, E.

AU - Kim, S.

AU - Akyol, T.

AU - Jamil, M.

AU - Shahrjerdi, Davood

AU - Donnelly, J.

AU - Colombo, L.

PY - 2009

Y1 - 2009

N2 - It is well known that the existence of a high quality oxide on Si has been key to the success of Si metal oxide semiconductor field effect transistors (MOSFETs). Scaling of Si CMOS logic devices to the next level has led to a flurry of activity in enhanced channel mobility materials such as III-V, Ge, and graphene. Since these materials lack a high-quality native oxide, integrating high-k gate dielectrics is necessary. Atomic layer deposition (ALD) offers precise control over the uniformity and thickness of the deposited high-k films through as well as reduction of native oxides by appropriate chemistry. Nevertheless, integrating ALD high-k on Ge, graphene and III-V materials necessitates the use of an effective chemical surface treatment protocol. This is to alter the surface properties in order to ensure full surface coverage, while preventing the re-growth of native oxides during the ex-situ sample transfer into the ALD reactor.

AB - It is well known that the existence of a high quality oxide on Si has been key to the success of Si metal oxide semiconductor field effect transistors (MOSFETs). Scaling of Si CMOS logic devices to the next level has led to a flurry of activity in enhanced channel mobility materials such as III-V, Ge, and graphene. Since these materials lack a high-quality native oxide, integrating high-k gate dielectrics is necessary. Atomic layer deposition (ALD) offers precise control over the uniformity and thickness of the deposited high-k films through as well as reduction of native oxides by appropriate chemistry. Nevertheless, integrating ALD high-k on Ge, graphene and III-V materials necessitates the use of an effective chemical surface treatment protocol. This is to alter the surface properties in order to ensure full surface coverage, while preventing the re-growth of native oxides during the ex-situ sample transfer into the ALD reactor.

UR - http://www.scopus.com/inward/record.url?scp=76549110798&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=76549110798&partnerID=8YFLogxK

U2 - 10.1149/1.3206627

DO - 10.1149/1.3206627

M3 - Conference contribution

SN - 9781566777438

VL - 25

SP - 285

EP - 299

BT - ECS Transactions - Physics and Technology of High-k Gate Dielectrics 7

ER -