HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors

Yatish Turakhia, Bharathwaj Raghunathan, Siddharth Garg, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose an efficient iterative optimization based approach for architectural synthesis of dark silicon heterogeneous chip multi-processors (CMPs). The goal is to determine the optimal number of cores of each type to provision the CMP with, such that the area and power budgets are met and the application performance is maximized. We consider general-purpose multi-threaded applications with a varying degree of parallelism (DOP) that can be set at run-time, and propose an accurate analytical model to predict the execution time of such applications on heterogeneous CMPs. Our experimental results illustrate that the synthesized heterogeneous dark silicon CMPs provide between 19% to 60% performance improvements over conventional homogeneous designs for variable and fixed DOP scenarios, respectively.

Original languageEnglish (US)
Title of host publicationProceedings of the 50th Annual Design Automation Conference, DAC 2013
Pages1-6
Number of pages6
DOIs
StatePublished - 2013
Event50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States
Duration: May 29 2013Jun 7 2013

Other

Other50th Annual Design Automation Conference, DAC 2013
CountryUnited States
CityAustin, TX
Period5/29/136/7/13

Fingerprint

Chip multiprocessors
Silicon
Synthesis
Parallelism
Analytical models
Analytical Model
Execution Time
Predict
Scenarios
Architecture
Optimization
Experimental Results

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Turakhia, Y., Raghunathan, B., Garg, S., & Marculescu, D. (2013). HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors. In Proceedings of the 50th Annual Design Automation Conference, DAC 2013 (pp. 1-6). [173] https://doi.org/10.1145/2463209.2488948

HaDeS : Architectural synthesis for heterogeneous dark silicon chip multi-processors. / Turakhia, Yatish; Raghunathan, Bharathwaj; Garg, Siddharth; Marculescu, Diana.

Proceedings of the 50th Annual Design Automation Conference, DAC 2013. 2013. p. 1-6 173.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Turakhia, Y, Raghunathan, B, Garg, S & Marculescu, D 2013, HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors. in Proceedings of the 50th Annual Design Automation Conference, DAC 2013., 173, pp. 1-6, 50th Annual Design Automation Conference, DAC 2013, Austin, TX, United States, 5/29/13. https://doi.org/10.1145/2463209.2488948
Turakhia Y, Raghunathan B, Garg S, Marculescu D. HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors. In Proceedings of the 50th Annual Design Automation Conference, DAC 2013. 2013. p. 1-6. 173 https://doi.org/10.1145/2463209.2488948
Turakhia, Yatish ; Raghunathan, Bharathwaj ; Garg, Siddharth ; Marculescu, Diana. / HaDeS : Architectural synthesis for heterogeneous dark silicon chip multi-processors. Proceedings of the 50th Annual Design Automation Conference, DAC 2013. 2013. pp. 1-6
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