Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Ali Khakifirooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam Shahidi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1-5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.

Original languageEnglish (US)
Title of host publication2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
Pages152-153
Number of pages2
Volume53
DOIs
StatePublished - 2010
Event2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
Duration: Feb 7 2010Feb 11 2010

Other

Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
CountryUnited States
CitySan Francisco, CA
Period2/7/102/11/10

Fingerprint

Doping (additives)
Gate dielectrics
Static random access storage
Electric potential
Silicon
Threshold voltage
Leakage currents
Tuning
Modulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Khakifirooz, A., Cheng, K., Jagannathan, B., Kulkarni, P., Sleight, J. W., Shahrjerdi, D., ... Shahidi, G. (2010). Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (Vol. 53, pp. 152-153). [5434014] https://doi.org/10.1109/ISSCC.2010.5434014

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. / Khakifirooz, Ali; Cheng, Kangguo; Jagannathan, Basanth; Kulkarni, Pranita; Sleight, Jeffrey W.; Shahrjerdi, Davood; Chang, Josephine B.; Lee, Sungjae; Li, Junjun; Bu, Huiming; Gauthier, Robert; Doris, Bruce; Shahidi, Ghavam.

2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. Vol. 53 2010. p. 152-153 5434014.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Khakifirooz, A, Cheng, K, Jagannathan, B, Kulkarni, P, Sleight, JW, Shahrjerdi, D, Chang, JB, Lee, S, Li, J, Bu, H, Gauthier, R, Doris, B & Shahidi, G 2010, Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. in 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. vol. 53, 5434014, pp. 152-153, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, CA, United States, 2/7/10. https://doi.org/10.1109/ISSCC.2010.5434014
Khakifirooz A, Cheng K, Jagannathan B, Kulkarni P, Sleight JW, Shahrjerdi D et al. Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. Vol. 53. 2010. p. 152-153. 5434014 https://doi.org/10.1109/ISSCC.2010.5434014
Khakifirooz, Ali ; Cheng, Kangguo ; Jagannathan, Basanth ; Kulkarni, Pranita ; Sleight, Jeffrey W. ; Shahrjerdi, Davood ; Chang, Josephine B. ; Lee, Sungjae ; Li, Junjun ; Bu, Huiming ; Gauthier, Robert ; Doris, Bruce ; Shahidi, Ghavam. / Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. Vol. 53 2010. pp. 152-153
@inproceedings{5c7cc4c88909445bb72b0ba260e53f62,
title = "Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond",
abstract = "Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1-5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.",
author = "Ali Khakifirooz and Kangguo Cheng and Basanth Jagannathan and Pranita Kulkarni and Sleight, {Jeffrey W.} and Davood Shahrjerdi and Chang, {Josephine B.} and Sungjae Lee and Junjun Li and Huiming Bu and Robert Gauthier and Bruce Doris and Ghavam Shahidi",
year = "2010",
doi = "10.1109/ISSCC.2010.5434014",
language = "English (US)",
isbn = "9781424460342",
volume = "53",
pages = "152--153",
booktitle = "2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers",

}

TY - GEN

T1 - Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

AU - Khakifirooz, Ali

AU - Cheng, Kangguo

AU - Jagannathan, Basanth

AU - Kulkarni, Pranita

AU - Sleight, Jeffrey W.

AU - Shahrjerdi, Davood

AU - Chang, Josephine B.

AU - Lee, Sungjae

AU - Li, Junjun

AU - Bu, Huiming

AU - Gauthier, Robert

AU - Doris, Bruce

AU - Shahidi, Ghavam

PY - 2010

Y1 - 2010

N2 - Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1-5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.

AB - Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1-5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.

UR - http://www.scopus.com/inward/record.url?scp=77952192381&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77952192381&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2010.5434014

DO - 10.1109/ISSCC.2010.5434014

M3 - Conference contribution

SN - 9781424460342

VL - 53

SP - 152

EP - 153

BT - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers

ER -