FPGA controlled WDM buffer memory

L. Wu, H. J. Chao, X. J. Zhao, Y. Zhao, Y. Chai, J. P. Zhang, F. S. Choa

Research output: Contribution to conferencePaper

Abstract

An overview is given on a recent work on a WDM loop memory controlled by an FPGA (Field Programmable Gate Array) chip. The WDM loop memory is designed for use in a 4 × 4 shared-memory multicast switch.

Original languageEnglish (US)
Pages340-341
Number of pages2
DOIs
StatePublished - Jan 1 2000
EventConference on Lasers and Electro-Optics (CLEO 2000) - San Francisco, CA, USA
Duration: May 7 2000May 12 2000

Other

OtherConference on Lasers and Electro-Optics (CLEO 2000)
CitySan Francisco, CA, USA
Period5/7/005/12/00

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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  • Cite this

    Wu, L., Chao, H. J., Zhao, X. J., Zhao, Y., Chai, Y., Zhang, J. P., & Choa, F. S. (2000). FPGA controlled WDM buffer memory. 340-341. Paper presented at Conference on Lasers and Electro-Optics (CLEO 2000), San Francisco, CA, USA, . https://doi.org/10.1109/cleo.2000.907089