Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage

Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Globalization of the system-on-chip (SoC) design flow has created opportunities for rogue intellectual property (IP) vendors to insert malicious circuits (a.k.a. hardware Trojans) into their IPs. We propose to formally verify third party IPs (3PIPs) for unauthorized information leakage. We validate our technique using Trojan benchmarks from the Trust-Hub.

Original languageEnglish (US)
Title of host publicationProceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems
PublisherIEEE Computer Society
Pages547-552
Number of pages6
Volume2016-March
ISBN (Print)9781467387002
DOIs
StatePublished - Mar 16 2016
Event29th International Conference on VLSI Design, VLSID 2016 - Kolkata, India
Duration: Jan 4 2016Jan 8 2016

Other

Other29th International Conference on VLSI Design, VLSID 2016
CountryIndia
CityKolkata
Period1/4/161/8/16

Fingerprint

Intellectual property
Hardware
Networks (circuits)
Intellectual property core
System-on-chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Rajendran, J., Dhandayuthapany, A. M., Vedula, V., & Karri, R. (2016). Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. In Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems (Vol. 2016-March, pp. 547-552). [7435011] IEEE Computer Society. https://doi.org/10.1109/VLSID.2016.143

Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. / Rajendran, Jeyavijayan; Dhandayuthapany, Arunshankar Muruga; Vedula, Vivekananda; Karri, Ramesh.

Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems. Vol. 2016-March IEEE Computer Society, 2016. p. 547-552 7435011.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rajendran, J, Dhandayuthapany, AM, Vedula, V & Karri, R 2016, Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. in Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems. vol. 2016-March, 7435011, IEEE Computer Society, pp. 547-552, 29th International Conference on VLSI Design, VLSID 2016, Kolkata, India, 1/4/16. https://doi.org/10.1109/VLSID.2016.143
Rajendran J, Dhandayuthapany AM, Vedula V, Karri R. Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. In Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems. Vol. 2016-March. IEEE Computer Society. 2016. p. 547-552. 7435011 https://doi.org/10.1109/VLSID.2016.143
Rajendran, Jeyavijayan ; Dhandayuthapany, Arunshankar Muruga ; Vedula, Vivekananda ; Karri, Ramesh. / Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems. Vol. 2016-March IEEE Computer Society, 2016. pp. 547-552
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