Fault tolerant Quantum Cellular Array (QCA) design using Triple Modular Redundancy with Shifted Operands

Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Due to their extremely small feature sizes and ultra low power consumption, Quantum-dot Cellular Automata (QCA) technology is projected to be a promising nanotechnology. However, in nanotechnologies, manufacture time defect levels and operational time fault rates are expected to be quite high. Straightforward Triple Modular Redundancy (TMR) based fault tolerance is inappropriate for QCA nanotechnology since wire delays dominate the logic delays and faults in wires dominate the faults in a QCA based design. Furthermore, long wires are necessary in TMR based designs. In this paper we show that fault-tolerance can be obtained by using TMR with Shifted Operands (TMRSO). TMRSO uses shorter wires of QCA cells and exploits the self-latching property of clocked QCA arrays to provide the same level of fault tolerance capability as straightforward TMR while being significantly faster and smaller. This technique can be applied to a variety of operations; we have validated TMRSO on adders. Implementation results obtained using QCADesigner [6] show that an 8-bit adder using TMRSO has more than 50% area reduction and more than 100% throughput improvement when compared to a TMR implementation.

Original languageEnglish (US)
Title of host publicationProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages1192-1195
Number of pages4
Volume2
StatePublished - 2005
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: Jan 18 2005Jan 21 2005

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period1/18/051/21/05

Fingerprint

Cellular arrays
Redundancy
Fault tolerance
Nanotechnology
Wire
Adders
Cellular automata
Semiconductor quantum dots
Electric power utilization
Throughput
Defects

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Wei, T., Wu, K., Karri, R., & Orailoglu, A. (2005). Fault tolerant Quantum Cellular Array (QCA) design using Triple Modular Redundancy with Shifted Operands. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (Vol. 2, pp. 1192-1195). [1466555]

Fault tolerant Quantum Cellular Array (QCA) design using Triple Modular Redundancy with Shifted Operands. / Wei, Tongquan; Wu, Kaijie; Karri, Ramesh; Orailoglu, Alex.

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Vol. 2 2005. p. 1192-1195 1466555.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wei, T, Wu, K, Karri, R & Orailoglu, A 2005, Fault tolerant Quantum Cellular Array (QCA) design using Triple Modular Redundancy with Shifted Operands. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. vol. 2, 1466555, pp. 1192-1195, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 1/18/05.
Wei T, Wu K, Karri R, Orailoglu A. Fault tolerant Quantum Cellular Array (QCA) design using Triple Modular Redundancy with Shifted Operands. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Vol. 2. 2005. p. 1192-1195. 1466555
Wei, Tongquan ; Wu, Kaijie ; Karri, Ramesh ; Orailoglu, Alex. / Fault tolerant Quantum Cellular Array (QCA) design using Triple Modular Redundancy with Shifted Operands. Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Vol. 2 2005. pp. 1192-1195
@inproceedings{ad73164be4cd429799ecc34f091aa869,
title = "Fault tolerant Quantum Cellular Array (QCA) design using Triple Modular Redundancy with Shifted Operands",
abstract = "Due to their extremely small feature sizes and ultra low power consumption, Quantum-dot Cellular Automata (QCA) technology is projected to be a promising nanotechnology. However, in nanotechnologies, manufacture time defect levels and operational time fault rates are expected to be quite high. Straightforward Triple Modular Redundancy (TMR) based fault tolerance is inappropriate for QCA nanotechnology since wire delays dominate the logic delays and faults in wires dominate the faults in a QCA based design. Furthermore, long wires are necessary in TMR based designs. In this paper we show that fault-tolerance can be obtained by using TMR with Shifted Operands (TMRSO). TMRSO uses shorter wires of QCA cells and exploits the self-latching property of clocked QCA arrays to provide the same level of fault tolerance capability as straightforward TMR while being significantly faster and smaller. This technique can be applied to a variety of operations; we have validated TMRSO on adders. Implementation results obtained using QCADesigner [6] show that an 8-bit adder using TMRSO has more than 50{\%} area reduction and more than 100{\%} throughput improvement when compared to a TMR implementation.",
author = "Tongquan Wei and Kaijie Wu and Ramesh Karri and Alex Orailoglu",
year = "2005",
language = "English (US)",
isbn = "0780387368",
volume = "2",
pages = "1192--1195",
booktitle = "Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005",

}

TY - GEN

T1 - Fault tolerant Quantum Cellular Array (QCA) design using Triple Modular Redundancy with Shifted Operands

AU - Wei, Tongquan

AU - Wu, Kaijie

AU - Karri, Ramesh

AU - Orailoglu, Alex

PY - 2005

Y1 - 2005

N2 - Due to their extremely small feature sizes and ultra low power consumption, Quantum-dot Cellular Automata (QCA) technology is projected to be a promising nanotechnology. However, in nanotechnologies, manufacture time defect levels and operational time fault rates are expected to be quite high. Straightforward Triple Modular Redundancy (TMR) based fault tolerance is inappropriate for QCA nanotechnology since wire delays dominate the logic delays and faults in wires dominate the faults in a QCA based design. Furthermore, long wires are necessary in TMR based designs. In this paper we show that fault-tolerance can be obtained by using TMR with Shifted Operands (TMRSO). TMRSO uses shorter wires of QCA cells and exploits the self-latching property of clocked QCA arrays to provide the same level of fault tolerance capability as straightforward TMR while being significantly faster and smaller. This technique can be applied to a variety of operations; we have validated TMRSO on adders. Implementation results obtained using QCADesigner [6] show that an 8-bit adder using TMRSO has more than 50% area reduction and more than 100% throughput improvement when compared to a TMR implementation.

AB - Due to their extremely small feature sizes and ultra low power consumption, Quantum-dot Cellular Automata (QCA) technology is projected to be a promising nanotechnology. However, in nanotechnologies, manufacture time defect levels and operational time fault rates are expected to be quite high. Straightforward Triple Modular Redundancy (TMR) based fault tolerance is inappropriate for QCA nanotechnology since wire delays dominate the logic delays and faults in wires dominate the faults in a QCA based design. Furthermore, long wires are necessary in TMR based designs. In this paper we show that fault-tolerance can be obtained by using TMR with Shifted Operands (TMRSO). TMRSO uses shorter wires of QCA cells and exploits the self-latching property of clocked QCA arrays to provide the same level of fault tolerance capability as straightforward TMR while being significantly faster and smaller. This technique can be applied to a variety of operations; we have validated TMRSO on adders. Implementation results obtained using QCADesigner [6] show that an 8-bit adder using TMRSO has more than 50% area reduction and more than 100% throughput improvement when compared to a TMR implementation.

UR - http://www.scopus.com/inward/record.url?scp=84861448153&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84861448153&partnerID=8YFLogxK

M3 - Conference contribution

SN - 0780387368

SN - 9780780387362

VL - 2

SP - 1192

EP - 1195

BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

ER -