Fault tolerant approaches to nanoelectronic programmable logic arrays

Wenjing Rao, Alex Orailoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly regular structure compatible with the nano crossbar architectures. Reliability is an important challenge as far as nanoelectronic devices are concerned. Consequently, it is necessary to focus on the fault tolerance aspects of nanoelectronic PLAs to ensure their viability as a foundation for nanoelectronic systems. In this paper, we investigate two types of fault tolerance techniques for nanoelectronic device based PLAs, focusing at the online faults occurring at the cross-points of nano devices. We develop a scheme to precisely locate the faults online, as this is a crucial step for efficient online reconfiguration based fault tolerance schemes. We also propose a tautology based fault masking scheme. We demonstrate that these two types of fault tolerance schemes developed for nano PLAs significantly improve at low hardware cost the reliability of the high fault occurrence nanoelectronic environment.

Original languageEnglish (US)
Title of host publicationProceedings - 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007
Pages216-223
Number of pages8
DOIs
StatePublished - 2007
Event37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007 - Edinburgh, United Kingdom
Duration: Jun 25 2007Jun 28 2007

Other

Other37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007
CountryUnited Kingdom
CityEdinburgh
Period6/25/076/28/07

Fingerprint

Nanoelectronics
Fault tolerance
Hardware
Costs

ASJC Scopus subject areas

  • Computer Science (miscellaneous)
  • Computer Networks and Communications

Cite this

Rao, W., Orailoglu, A., & Karri, R. (2007). Fault tolerant approaches to nanoelectronic programmable logic arrays. In Proceedings - 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007 (pp. 216-223). [4272973] https://doi.org/10.1109/DSN.2007.49

Fault tolerant approaches to nanoelectronic programmable logic arrays. / Rao, Wenjing; Orailoglu, Alex; Karri, Ramesh.

Proceedings - 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007. 2007. p. 216-223 4272973.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rao, W, Orailoglu, A & Karri, R 2007, Fault tolerant approaches to nanoelectronic programmable logic arrays. in Proceedings - 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007., 4272973, pp. 216-223, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007, Edinburgh, United Kingdom, 6/25/07. https://doi.org/10.1109/DSN.2007.49
Rao W, Orailoglu A, Karri R. Fault tolerant approaches to nanoelectronic programmable logic arrays. In Proceedings - 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007. 2007. p. 216-223. 4272973 https://doi.org/10.1109/DSN.2007.49
Rao, Wenjing ; Orailoglu, Alex ; Karri, Ramesh. / Fault tolerant approaches to nanoelectronic programmable logic arrays. Proceedings - 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007. 2007. pp. 216-223
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