Fault secure datapath synthesis using hybrid time and hardware redundancy

Kaijie Wu, Ramesh Karri

Research output: Contribution to journalArticle

Abstract

A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can tradeoff time and hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys' Behavioral Compiler.

Original languageEnglish (US)
Pages (from-to)1476-1484
Number of pages9
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume23
Issue number10
DOIs
StatePublished - Oct 2004

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Redundancy
Hardware
Error detection

Keywords

  • Concurrent error detection (CED)
  • Fault secure datapath
  • Register transfer (RT) level synthesis
  • Single event upset (SEU)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Science Applications
  • Computational Theory and Mathematics

Cite this

Fault secure datapath synthesis using hybrid time and hardware redundancy. / Wu, Kaijie; Karri, Ramesh.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 10, 10.2004, p. 1476-1484.

Research output: Contribution to journalArticle

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