Abstract
A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can tradeoff time and hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys' Behavioral Compiler.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1476-1484 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 23 |
| Issue number | 10 |
| DOIs | |
| State | Published - Oct 2004 |
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Keywords
- Concurrent error detection (CED)
- Fault secure datapath
- Register transfer (RT) level synthesis
- Single event upset (SEU)
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Computer Science Applications
- Computational Theory and Mathematics
Cite this
Fault secure datapath synthesis using hybrid time and hardware redundancy. / Wu, Kaijie; Karri, Ramesh.
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 10, 10.2004, p. 1476-1484.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Fault secure datapath synthesis using hybrid time and hardware redundancy
AU - Wu, Kaijie
AU - Karri, Ramesh
PY - 2004/10
Y1 - 2004/10
N2 - A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can tradeoff time and hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys' Behavioral Compiler.
AB - A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can tradeoff time and hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys' Behavioral Compiler.
KW - Concurrent error detection (CED)
KW - Fault secure datapath
KW - Register transfer (RT) level synthesis
KW - Single event upset (SEU)
UR - http://www.scopus.com/inward/record.url?scp=5444255060&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=5444255060&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2004.835132
DO - 10.1109/TCAD.2004.835132
M3 - Article
AN - SCOPUS:5444255060
VL - 23
SP - 1476
EP - 1484
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 10
ER -