Fault Analysis-Based Logic Encryption

Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett S. Rose, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri

Research output: Contribution to journalArticle

Abstract

Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately $4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design, but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.

Original languageEnglish (US)
Article number6616532
Pages (from-to)410-424
Number of pages15
JournalIEEE Transactions on Computers
Volume64
Issue number2
DOIs
StatePublished - Feb 1 2015

Fingerprint

Fault Analysis
Encryption
Cryptography
Logic
Hamming distance
Integrated Circuits
Output
Supply chains
Hamming Distance
Integrated circuit testing
Supply Chain
Attack
Industry
Target
Globalization
Circuit Design
Integrated circuits
Hardware
Fault
Maximise

Keywords

  • Automatic test pattern generation
  • combinational logic circuit
  • hardware security
  • IC piracy
  • integrated circuit testing
  • IP piracy
  • logic obfuscation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Computational Theory and Mathematics
  • Theoretical Computer Science

Cite this

Rajendran, J., Zhang, H., Zhang, C., Rose, G. S., Pino, Y., Sinanoglu, O., & Karri, R. (2015). Fault Analysis-Based Logic Encryption. IEEE Transactions on Computers, 64(2), 410-424. [6616532]. https://doi.org/10.1109/TC.2013.193

Fault Analysis-Based Logic Encryption. / Rajendran, Jeyavijayan; Zhang, Huan; Zhang, Chi; Rose, Garrett S.; Pino, Youngok; Sinanoglu, Ozgur; Karri, Ramesh.

In: IEEE Transactions on Computers, Vol. 64, No. 2, 6616532, 01.02.2015, p. 410-424.

Research output: Contribution to journalArticle

Rajendran, J, Zhang, H, Zhang, C, Rose, GS, Pino, Y, Sinanoglu, O & Karri, R 2015, 'Fault Analysis-Based Logic Encryption', IEEE Transactions on Computers, vol. 64, no. 2, 6616532, pp. 410-424. https://doi.org/10.1109/TC.2013.193
Rajendran J, Zhang H, Zhang C, Rose GS, Pino Y, Sinanoglu O et al. Fault Analysis-Based Logic Encryption. IEEE Transactions on Computers. 2015 Feb 1;64(2):410-424. 6616532. https://doi.org/10.1109/TC.2013.193
Rajendran, Jeyavijayan ; Zhang, Huan ; Zhang, Chi ; Rose, Garrett S. ; Pino, Youngok ; Sinanoglu, Ozgur ; Karri, Ramesh. / Fault Analysis-Based Logic Encryption. In: IEEE Transactions on Computers. 2015 ; Vol. 64, No. 2. pp. 410-424.
@article{af5194aae9584d98adb2c24a6260ef12,
title = "Fault Analysis-Based Logic Encryption",
abstract = "Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately $4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design, but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50{\%} Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50{\%} Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.",
keywords = "Automatic test pattern generation, combinational logic circuit, hardware security, IC piracy, integrated circuit testing, IP piracy, logic obfuscation",
author = "Jeyavijayan Rajendran and Huan Zhang and Chi Zhang and Rose, {Garrett S.} and Youngok Pino and Ozgur Sinanoglu and Ramesh Karri",
year = "2015",
month = "2",
day = "1",
doi = "10.1109/TC.2013.193",
language = "English (US)",
volume = "64",
pages = "410--424",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "2",

}

TY - JOUR

T1 - Fault Analysis-Based Logic Encryption

AU - Rajendran, Jeyavijayan

AU - Zhang, Huan

AU - Zhang, Chi

AU - Rose, Garrett S.

AU - Pino, Youngok

AU - Sinanoglu, Ozgur

AU - Karri, Ramesh

PY - 2015/2/1

Y1 - 2015/2/1

N2 - Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately $4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design, but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.

AB - Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately $4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design, but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.

KW - Automatic test pattern generation

KW - combinational logic circuit

KW - hardware security

KW - IC piracy

KW - integrated circuit testing

KW - IP piracy

KW - logic obfuscation

UR - http://www.scopus.com/inward/record.url?scp=84975319250&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84975319250&partnerID=8YFLogxK

U2 - 10.1109/TC.2013.193

DO - 10.1109/TC.2013.193

M3 - Article

AN - SCOPUS:84975319250

VL - 64

SP - 410

EP - 424

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 2

M1 - 6616532

ER -