Fast and energy-frugal deterministic test through test vector correlation exploitation

Ozgur Sinanoglu, A. Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthermore, the transitions that occur in the scan chains during these shifts reflect into significant levels of circuit switching unnecessarily, increasing the power dissipated. Judicious encoding of the correlation among the test vectors and construction of a test vector through predecessor updates helps reduce not only test application time but also scan chain transitions as well. Such an encoding scheme, which additionally reduces test data volume, can be further enhanced through appropriately ordering and padding of the test cubes given. The experimental results confirm the significant reductions in test application time, test data volume and test power achieved by the proposed compression methodology.

Original languageEnglish (US)
Title of host publicationProceediings - 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages325-333
Number of pages9
Volume2002-January
ISBN (Electronic)0769518311
DOIs
StatePublished - Jan 1 2002
Event17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002 - Vancouver, Canada
Duration: Nov 6 2002Nov 8 2002

Other

Other17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002
CountryCanada
CityVancouver
Period11/6/0211/8/02

Fingerprint

Switching circuits
Flip flop circuits
Networks (circuits)

Keywords

  • Application software
  • Circuit testing
  • Computer science
  • Encoding
  • Flip-flops
  • Power dissipation
  • Power engineering and energy
  • Shift registers
  • Switching circuits
  • System-on-a-chip

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Sinanoglu, O., & Orailoglu, A. (2002). Fast and energy-frugal deterministic test through test vector correlation exploitation. In Proceediings - 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002 (Vol. 2002-January, pp. 325-333). [1173529] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFTVS.2002.1173529

Fast and energy-frugal deterministic test through test vector correlation exploitation. / Sinanoglu, Ozgur; Orailoglu, A.

Proceediings - 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. p. 325-333 1173529.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sinanoglu, O & Orailoglu, A 2002, Fast and energy-frugal deterministic test through test vector correlation exploitation. in Proceediings - 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002. vol. 2002-January, 1173529, Institute of Electrical and Electronics Engineers Inc., pp. 325-333, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002, Vancouver, Canada, 11/6/02. https://doi.org/10.1109/DFTVS.2002.1173529
Sinanoglu O, Orailoglu A. Fast and energy-frugal deterministic test through test vector correlation exploitation. In Proceediings - 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002. Vol. 2002-January. Institute of Electrical and Electronics Engineers Inc. 2002. p. 325-333. 1173529 https://doi.org/10.1109/DFTVS.2002.1173529
Sinanoglu, Ozgur ; Orailoglu, A. / Fast and energy-frugal deterministic test through test vector correlation exploitation. Proceediings - 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. pp. 325-333
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