Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, Davood Shahrjerdi, L. F. Edge, A. Kimball, S. Kanakasabapathy, K. Xiu, S. Schmitz, A. Reznicek, T. Adam, H. He, N. Loubet, S. Holmes, S. Mehta, D. Yang, A. Upham, S. C. Seo & 16 others J. L. Herman, R. Johnson, Y. Zhu, P. Jamison, B. S. Haran, Z. Zhu, L. H. Vanamurth, S. Fan, D. Horak, H. Bu, P. J. Oldiges, D. K. Sadana, P. Kozlowski, D. McHerron, J. O'Neill, B. Doris

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 μA/μm, respectively, at Ioff = 300 pA/μm, V DD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV· μm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

Original languageEnglish (US)
Title of host publication2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
DOIs
StatePublished - 2009
Event2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States
Duration: Dec 7 2009Dec 9 2009

Other

Other2009 International Electron Devices Meeting, IEDM 2009
CountryUnited States
CityBaltimore, MD
Period12/7/0912/9/09

Fingerprint

SOI (semiconductors)
CMOS
chips
Gate dielectrics
Transconductance
Masks
Metals
boosters
transconductance
linings
acceleration (physics)
masks
analogs
System-on-chip
metals

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials
  • Materials Chemistry

Cite this

Cheng, K., Khakifirooz, A., Kulkarni, P., Ponoth, S., Kuss, J., Shahrjerdi, D., ... Doris, B. (2009). Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest [5424422] https://doi.org/10.1109/IEDM.2009.5424422

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. / Cheng, K.; Khakifirooz, A.; Kulkarni, P.; Ponoth, S.; Kuss, J.; Shahrjerdi, Davood; Edge, L. F.; Kimball, A.; Kanakasabapathy, S.; Xiu, K.; Schmitz, S.; Reznicek, A.; Adam, T.; He, H.; Loubet, N.; Holmes, S.; Mehta, S.; Yang, D.; Upham, A.; Seo, S. C.; Herman, J. L.; Johnson, R.; Zhu, Y.; Jamison, P.; Haran, B. S.; Zhu, Z.; Vanamurth, L. H.; Fan, S.; Horak, D.; Bu, H.; Oldiges, P. J.; Sadana, D. K.; Kozlowski, P.; McHerron, D.; O'Neill, J.; Doris, B.

2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. 5424422.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cheng, K, Khakifirooz, A, Kulkarni, P, Ponoth, S, Kuss, J, Shahrjerdi, D, Edge, LF, Kimball, A, Kanakasabapathy, S, Xiu, K, Schmitz, S, Reznicek, A, Adam, T, He, H, Loubet, N, Holmes, S, Mehta, S, Yang, D, Upham, A, Seo, SC, Herman, JL, Johnson, R, Zhu, Y, Jamison, P, Haran, BS, Zhu, Z, Vanamurth, LH, Fan, S, Horak, D, Bu, H, Oldiges, PJ, Sadana, DK, Kozlowski, P, McHerron, D, O'Neill, J & Doris, B 2009, Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. in 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest., 5424422, 2009 International Electron Devices Meeting, IEDM 2009, Baltimore, MD, United States, 12/7/09. https://doi.org/10.1109/IEDM.2009.5424422
Cheng K, Khakifirooz A, Kulkarni P, Ponoth S, Kuss J, Shahrjerdi D et al. Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. 5424422 https://doi.org/10.1109/IEDM.2009.5424422
Cheng, K. ; Khakifirooz, A. ; Kulkarni, P. ; Ponoth, S. ; Kuss, J. ; Shahrjerdi, Davood ; Edge, L. F. ; Kimball, A. ; Kanakasabapathy, S. ; Xiu, K. ; Schmitz, S. ; Reznicek, A. ; Adam, T. ; He, H. ; Loubet, N. ; Holmes, S. ; Mehta, S. ; Yang, D. ; Upham, A. ; Seo, S. C. ; Herman, J. L. ; Johnson, R. ; Zhu, Y. ; Jamison, P. ; Haran, B. S. ; Zhu, Z. ; Vanamurth, L. H. ; Fan, S. ; Horak, D. ; Bu, H. ; Oldiges, P. J. ; Sadana, D. K. ; Kozlowski, P. ; McHerron, D. ; O'Neill, J. ; Doris, B. / Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009.
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abstract = "We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 μA/μm, respectively, at Ioff = 300 pA/μm, V DD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV· μm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.",
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AU - Cheng, K.

AU - Khakifirooz, A.

AU - Kulkarni, P.

AU - Ponoth, S.

AU - Kuss, J.

AU - Shahrjerdi, Davood

AU - Edge, L. F.

AU - Kimball, A.

AU - Kanakasabapathy, S.

AU - Xiu, K.

AU - Schmitz, S.

AU - Reznicek, A.

AU - Adam, T.

AU - He, H.

AU - Loubet, N.

AU - Holmes, S.

AU - Mehta, S.

AU - Yang, D.

AU - Upham, A.

AU - Seo, S. C.

AU - Herman, J. L.

AU - Johnson, R.

AU - Zhu, Y.

AU - Jamison, P.

AU - Haran, B. S.

AU - Zhu, Z.

AU - Vanamurth, L. H.

AU - Fan, S.

AU - Horak, D.

AU - Bu, H.

AU - Oldiges, P. J.

AU - Sadana, D. K.

AU - Kozlowski, P.

AU - McHerron, D.

AU - O'Neill, J.

AU - Doris, B.

PY - 2009

Y1 - 2009

N2 - We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 μA/μm, respectively, at Ioff = 300 pA/μm, V DD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV· μm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

AB - We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 μA/μm, respectively, at Ioff = 300 pA/μm, V DD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV· μm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

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U2 - 10.1109/IEDM.2009.5424422

DO - 10.1109/IEDM.2009.5424422

M3 - Conference contribution

SN - 9781424456406

BT - 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest

ER -