Extending the applicability of parallel-serial scan designs

Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu

Research output: Contribution to journalConference article

Abstract

Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propose two different methodologies for test cost reduction in scan-based designs. The first methodology improves on the Illinois Scan Architecture, aiming at reducing the high test cost of the test vectors that necessitate the serial test application mode. The second methodology employs on-chip serial transformations to generate an input stimulus that can be applied efficiently. The transformation-based methodology utilizes the proposed scan design to obtain the minimal cost input stimulus. The experimental results indicate that a substantial test cost reduction, reaching 90% levels, can be obtained.

Original languageEnglish (US)
Pages (from-to)200-203
Number of pages4
JournalProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
StatePublished - Dec 1 2004
EventProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States
Duration: Oct 11 2004Oct 13 2004

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Cost reduction
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Extending the applicability of parallel-serial scan designs. / Arslan, Baris; Sinanoglu, Ozgur; Orailoglu, Alex.

In: Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 01.12.2004, p. 200-203.

Research output: Contribution to journalConference article

@article{4ac3d3e311934ef8a68fb8b79aafa917,
title = "Extending the applicability of parallel-serial scan designs",
abstract = "Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propose two different methodologies for test cost reduction in scan-based designs. The first methodology improves on the Illinois Scan Architecture, aiming at reducing the high test cost of the test vectors that necessitate the serial test application mode. The second methodology employs on-chip serial transformations to generate an input stimulus that can be applied efficiently. The transformation-based methodology utilizes the proposed scan design to obtain the minimal cost input stimulus. The experimental results indicate that a substantial test cost reduction, reaching 90{\%} levels, can be obtained.",
author = "Baris Arslan and Ozgur Sinanoglu and Alex Orailoglu",
year = "2004",
month = "12",
day = "1",
language = "English (US)",
pages = "200--203",
journal = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",
issn = "1063-6404",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Extending the applicability of parallel-serial scan designs

AU - Arslan, Baris

AU - Sinanoglu, Ozgur

AU - Orailoglu, Alex

PY - 2004/12/1

Y1 - 2004/12/1

N2 - Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propose two different methodologies for test cost reduction in scan-based designs. The first methodology improves on the Illinois Scan Architecture, aiming at reducing the high test cost of the test vectors that necessitate the serial test application mode. The second methodology employs on-chip serial transformations to generate an input stimulus that can be applied efficiently. The transformation-based methodology utilizes the proposed scan design to obtain the minimal cost input stimulus. The experimental results indicate that a substantial test cost reduction, reaching 90% levels, can be obtained.

AB - Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propose two different methodologies for test cost reduction in scan-based designs. The first methodology improves on the Illinois Scan Architecture, aiming at reducing the high test cost of the test vectors that necessitate the serial test application mode. The second methodology employs on-chip serial transformations to generate an input stimulus that can be applied efficiently. The transformation-based methodology utilizes the proposed scan design to obtain the minimal cost input stimulus. The experimental results indicate that a substantial test cost reduction, reaching 90% levels, can be obtained.

UR - http://www.scopus.com/inward/record.url?scp=17644393923&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=17644393923&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:17644393923

SP - 200

EP - 203

JO - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

JF - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

SN - 1063-6404

ER -