Expedited response compaction for scan power reduction

Samah Mohamed Saeed, Ozgur Sinanoglu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Transitions embedded in between consecutive stimulus/response bits toggle scan cells during shift operations. The consequent switching activity in the scan chains further propagate into the combinational logic, resulting in elevated power dissipation levels, and thus, endangering the reliability of the chip being tested. Based on the observation that the content of scan chains during shift operations is irrelevant and unimportant, we propose an expedited response compaction technique in order to reduce power dissipation during scan operations. Parallelized (and expedited) compaction operations help compress the entire capture response onto a single reference chain during the first portion of shift cycles, enabling a simultaneous constant-0 feed to all the remaining chains, in which no scan-out power is dissipated during the subsequent shift cycles. This DfT-based approach is nonintrusive for design flow, requires a very minor investment in area, and in turn delivers significant savings in test power. The proposed solution reduces test power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction, while retaining the observed responses intact. Experimental results justify the efficacy of the proposed technique in attaining test power reductions.

    Original languageEnglish (US)
    Title of host publicationProceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011
    Pages40-45
    Number of pages6
    DOIs
    StatePublished - Jul 1 2011
    Event2011 29th IEEE VLSI Test Symposium, VTS 2011 - Dana Point, CA, United States
    Duration: May 1 2011May 5 2011

    Other

    Other2011 29th IEEE VLSI Test Symposium, VTS 2011
    CountryUnited States
    CityDana Point, CA
    Period5/1/115/5/11

    Fingerprint

    Energy dissipation
    Compaction

    ASJC Scopus subject areas

    • Computer Science Applications
    • Electrical and Electronic Engineering

    Cite this

    Saeed, S. M., & Sinanoglu, O. (2011). Expedited response compaction for scan power reduction. In Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011 (pp. 40-45). [5783752] https://doi.org/10.1109/VTS.2011.5783752

    Expedited response compaction for scan power reduction. / Saeed, Samah Mohamed; Sinanoglu, Ozgur.

    Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 2011. p. 40-45 5783752.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Saeed, SM & Sinanoglu, O 2011, Expedited response compaction for scan power reduction. in Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011., 5783752, pp. 40-45, 2011 29th IEEE VLSI Test Symposium, VTS 2011, Dana Point, CA, United States, 5/1/11. https://doi.org/10.1109/VTS.2011.5783752
    Saeed SM, Sinanoglu O. Expedited response compaction for scan power reduction. In Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 2011. p. 40-45. 5783752 https://doi.org/10.1109/VTS.2011.5783752
    Saeed, Samah Mohamed ; Sinanoglu, Ozgur. / Expedited response compaction for scan power reduction. Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 2011. pp. 40-45
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