A recent trend has been low-power test solutions in the context of compression based scan architectures where filling of x's for higher compression and for lower power are two conflicting objectives. Test generation and/or x-filling solutions for addressing shift and/or capture power have attained reductions at the expense of an increase in pattern count, and thus in test costs. Lower scan-in power is the end-result, while the scan chains eventually receive the intended stimulus intact prior to capture; and, this technique works without clock gating. The shortcoming of the DB architecture  is that it only targets scan-in power reduction and overlooks scan-out power. Overwriting of the captured response upon its expedited compaction in all the other scan chains with shifted constant-0 values in turn delivers reductions in scan-out power. For industrial cases that employ 0-fill so as to eliminate transitions in stimuli, the proposed technique is 5 to 66 times more effective than DB in reducing average test power.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering