Error-resilient design of branch predictors for effective yield improvement

Sobeeh Almukhaizim, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Speculative execution methods have been long employed in microprocessors in order to boost their performance. Being speculative, their implementation is self-correcting functionally, as the speculation needs always to be verified, and, if incorrect, its effect nullified. Hence, the actions of a faulty speculative component self-correct, albeit at the cost of some performance degradation. As speculation techniques are aggressively employed to enhance microprocessor's performance, however, such performance faults may result in frequent violation of their expected speculation accuracy, significantly degrading the overall performance of the system. Hence, microprocessors with defective speculative components are discarded, resulting in yield loss. In this work, we propose several error-resilient design strategies for branch predictors; a representative example of speculative processor subsystems. The proposed methods support indexing mechanisms that can effectively re-map the history information, used for predicting branches, to fault-free entries, mitigating the impact of faults in heavily-used entries. Experimental results indicate that the proposed error-resilient design methods significantly reduce the impact of performance faults, effectively improving yield.

Original languageEnglish (US)
Title of host publicationLATW 2011 - 12th IEEE Latin-American Test Workshop
DOIs
StatePublished - Sep 15 2011
Event12th IEEE Latin-American Test Workshop, LATW 2011 - Porto de Galinhas, Brazil
Duration: Mar 27 2011Mar 30 2011

Other

Other12th IEEE Latin-American Test Workshop, LATW 2011
CountryBrazil
CityPorto de Galinhas
Period3/27/113/30/11

Fingerprint

Microprocessor chips
History
Degradation

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Almukhaizim, S., & Sinanoglu, O. (2011). Error-resilient design of branch predictors for effective yield improvement. In LATW 2011 - 12th IEEE Latin-American Test Workshop [5985910] https://doi.org/10.1109/LATW.2011.5985910

Error-resilient design of branch predictors for effective yield improvement. / Almukhaizim, Sobeeh; Sinanoglu, Ozgur.

LATW 2011 - 12th IEEE Latin-American Test Workshop. 2011. 5985910.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Almukhaizim, S & Sinanoglu, O 2011, Error-resilient design of branch predictors for effective yield improvement. in LATW 2011 - 12th IEEE Latin-American Test Workshop., 5985910, 12th IEEE Latin-American Test Workshop, LATW 2011, Porto de Galinhas, Brazil, 3/27/11. https://doi.org/10.1109/LATW.2011.5985910
Almukhaizim S, Sinanoglu O. Error-resilient design of branch predictors for effective yield improvement. In LATW 2011 - 12th IEEE Latin-American Test Workshop. 2011. 5985910 https://doi.org/10.1109/LATW.2011.5985910
Almukhaizim, Sobeeh ; Sinanoglu, Ozgur. / Error-resilient design of branch predictors for effective yield improvement. LATW 2011 - 12th IEEE Latin-American Test Workshop. 2011.
@inproceedings{986568cf42384831bf017e2f4e2bfb2f,
title = "Error-resilient design of branch predictors for effective yield improvement",
abstract = "Speculative execution methods have been long employed in microprocessors in order to boost their performance. Being speculative, their implementation is self-correcting functionally, as the speculation needs always to be verified, and, if incorrect, its effect nullified. Hence, the actions of a faulty speculative component self-correct, albeit at the cost of some performance degradation. As speculation techniques are aggressively employed to enhance microprocessor's performance, however, such performance faults may result in frequent violation of their expected speculation accuracy, significantly degrading the overall performance of the system. Hence, microprocessors with defective speculative components are discarded, resulting in yield loss. In this work, we propose several error-resilient design strategies for branch predictors; a representative example of speculative processor subsystems. The proposed methods support indexing mechanisms that can effectively re-map the history information, used for predicting branches, to fault-free entries, mitigating the impact of faults in heavily-used entries. Experimental results indicate that the proposed error-resilient design methods significantly reduce the impact of performance faults, effectively improving yield.",
author = "Sobeeh Almukhaizim and Ozgur Sinanoglu",
year = "2011",
month = "9",
day = "15",
doi = "10.1109/LATW.2011.5985910",
language = "English (US)",
isbn = "9781457714900",
booktitle = "LATW 2011 - 12th IEEE Latin-American Test Workshop",

}

TY - GEN

T1 - Error-resilient design of branch predictors for effective yield improvement

AU - Almukhaizim, Sobeeh

AU - Sinanoglu, Ozgur

PY - 2011/9/15

Y1 - 2011/9/15

N2 - Speculative execution methods have been long employed in microprocessors in order to boost their performance. Being speculative, their implementation is self-correcting functionally, as the speculation needs always to be verified, and, if incorrect, its effect nullified. Hence, the actions of a faulty speculative component self-correct, albeit at the cost of some performance degradation. As speculation techniques are aggressively employed to enhance microprocessor's performance, however, such performance faults may result in frequent violation of their expected speculation accuracy, significantly degrading the overall performance of the system. Hence, microprocessors with defective speculative components are discarded, resulting in yield loss. In this work, we propose several error-resilient design strategies for branch predictors; a representative example of speculative processor subsystems. The proposed methods support indexing mechanisms that can effectively re-map the history information, used for predicting branches, to fault-free entries, mitigating the impact of faults in heavily-used entries. Experimental results indicate that the proposed error-resilient design methods significantly reduce the impact of performance faults, effectively improving yield.

AB - Speculative execution methods have been long employed in microprocessors in order to boost their performance. Being speculative, their implementation is self-correcting functionally, as the speculation needs always to be verified, and, if incorrect, its effect nullified. Hence, the actions of a faulty speculative component self-correct, albeit at the cost of some performance degradation. As speculation techniques are aggressively employed to enhance microprocessor's performance, however, such performance faults may result in frequent violation of their expected speculation accuracy, significantly degrading the overall performance of the system. Hence, microprocessors with defective speculative components are discarded, resulting in yield loss. In this work, we propose several error-resilient design strategies for branch predictors; a representative example of speculative processor subsystems. The proposed methods support indexing mechanisms that can effectively re-map the history information, used for predicting branches, to fault-free entries, mitigating the impact of faults in heavily-used entries. Experimental results indicate that the proposed error-resilient design methods significantly reduce the impact of performance faults, effectively improving yield.

UR - http://www.scopus.com/inward/record.url?scp=80052622843&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052622843&partnerID=8YFLogxK

U2 - 10.1109/LATW.2011.5985910

DO - 10.1109/LATW.2011.5985910

M3 - Conference contribution

AN - SCOPUS:80052622843

SN - 9781457714900

BT - LATW 2011 - 12th IEEE Latin-American Test Workshop

ER -