Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators

Jeff Zhang, Zahra Ghodsi, Kartheek Rangineni, Siddharth Garg

Research output: Contribution to journalArticle

Abstract

Hardware accelerators are being increasingly deployed to boost the performance and energy efficiency of deep neural network (DNN) inference. In this paper we propose Thundervolt, a new framework that enables aggressive voltage underscaling for energy-efficient, systolic array (SA) based DNN accelerators without compromising classification accuracy even in the presence of high timing error rates. Using post-synthesis timing simulations of two commonly used SA accelerator architectures, we show that Thundervolt enables between 45%-50% energy savings on state-of-the-art speech and image recognition benchmarks with less than 1% loss in classification accuracy and no performance loss. Additionally, Thundervolt is robust against the impact of process variations. Finally, we show that Thundervolt is synergistic with and can further increase the energy efficiency of commonly used run-time DNN pruning techniques like Zero-Skip.

Original languageEnglish (US)
JournalIEEE Design and Test
DOIs
StateAccepted/In press - Jan 1 2019

Fingerprint

Systolic arrays
Particle accelerators
Energy efficiency
Image recognition
Speech recognition
Energy conservation
Hardware
Electric potential
Deep learning
Deep neural networks

Keywords

  • Deep Neural Network
  • Energy Efficiency
  • Hardware Accelerator
  • Systolic Arrays
  • Timing Error
  • Timing Speculation

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators. / Zhang, Jeff; Ghodsi, Zahra; Rangineni, Kartheek; Garg, Siddharth.

In: IEEE Design and Test, 01.01.2019.

Research output: Contribution to journalArticle

@article{46644ae1ff7e46a88edaff559c930bc1,
title = "Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators",
abstract = "Hardware accelerators are being increasingly deployed to boost the performance and energy efficiency of deep neural network (DNN) inference. In this paper we propose Thundervolt, a new framework that enables aggressive voltage underscaling for energy-efficient, systolic array (SA) based DNN accelerators without compromising classification accuracy even in the presence of high timing error rates. Using post-synthesis timing simulations of two commonly used SA accelerator architectures, we show that Thundervolt enables between 45{\%}-50{\%} energy savings on state-of-the-art speech and image recognition benchmarks with less than 1{\%} loss in classification accuracy and no performance loss. Additionally, Thundervolt is robust against the impact of process variations. Finally, we show that Thundervolt is synergistic with and can further increase the energy efficiency of commonly used run-time DNN pruning techniques like Zero-Skip.",
keywords = "Deep Neural Network, Energy Efficiency, Hardware Accelerator, Systolic Arrays, Timing Error, Timing Speculation",
author = "Jeff Zhang and Zahra Ghodsi and Kartheek Rangineni and Siddharth Garg",
year = "2019",
month = "1",
day = "1",
doi = "10.1109/MDAT.2019.2947271",
language = "English (US)",
journal = "IEEE Design and Test",
issn = "2168-2356",
publisher = "IEEE Computer Society",

}

TY - JOUR

T1 - Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators

AU - Zhang, Jeff

AU - Ghodsi, Zahra

AU - Rangineni, Kartheek

AU - Garg, Siddharth

PY - 2019/1/1

Y1 - 2019/1/1

N2 - Hardware accelerators are being increasingly deployed to boost the performance and energy efficiency of deep neural network (DNN) inference. In this paper we propose Thundervolt, a new framework that enables aggressive voltage underscaling for energy-efficient, systolic array (SA) based DNN accelerators without compromising classification accuracy even in the presence of high timing error rates. Using post-synthesis timing simulations of two commonly used SA accelerator architectures, we show that Thundervolt enables between 45%-50% energy savings on state-of-the-art speech and image recognition benchmarks with less than 1% loss in classification accuracy and no performance loss. Additionally, Thundervolt is robust against the impact of process variations. Finally, we show that Thundervolt is synergistic with and can further increase the energy efficiency of commonly used run-time DNN pruning techniques like Zero-Skip.

AB - Hardware accelerators are being increasingly deployed to boost the performance and energy efficiency of deep neural network (DNN) inference. In this paper we propose Thundervolt, a new framework that enables aggressive voltage underscaling for energy-efficient, systolic array (SA) based DNN accelerators without compromising classification accuracy even in the presence of high timing error rates. Using post-synthesis timing simulations of two commonly used SA accelerator architectures, we show that Thundervolt enables between 45%-50% energy savings on state-of-the-art speech and image recognition benchmarks with less than 1% loss in classification accuracy and no performance loss. Additionally, Thundervolt is robust against the impact of process variations. Finally, we show that Thundervolt is synergistic with and can further increase the energy efficiency of commonly used run-time DNN pruning techniques like Zero-Skip.

KW - Deep Neural Network

KW - Energy Efficiency

KW - Hardware Accelerator

KW - Systolic Arrays

KW - Timing Error

KW - Timing Speculation

UR - http://www.scopus.com/inward/record.url?scp=85073539087&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85073539087&partnerID=8YFLogxK

U2 - 10.1109/MDAT.2019.2947271

DO - 10.1109/MDAT.2019.2947271

M3 - Article

AN - SCOPUS:85073539087

JO - IEEE Design and Test

JF - IEEE Design and Test

SN - 2168-2356

ER -