Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators

Jeff Zhang, Zahra Ghodsi, Kartheek Rangineni, Siddharth Garg

Research output: Contribution to journalArticle

Abstract

Hardware accelerators are being increasingly deployed to boost the performance and energy efficiency of deep neural network (DNN) inference. In this paper we propose Thundervolt, a new framework that enables aggressive voltage underscaling for energy-efficient, systolic array (SA) based DNN accelerators without compromising classification accuracy even in the presence of high timing error rates. Using post-synthesis timing simulations of two commonly used SA accelerator architectures, we show that Thundervolt enables between 45%-50% energy savings on state-of-the-art speech and image recognition benchmarks with less than 1% loss in classification accuracy and no performance loss. Additionally, Thundervolt is robust against the impact of process variations. Finally, we show that Thundervolt is synergistic with and can further increase the energy efficiency of commonly used run-time DNN pruning techniques like Zero-Skip.

Original languageEnglish (US)
JournalIEEE Design and Test
DOIs
StateAccepted/In press - Jan 1 2019

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Keywords

  • Deep Neural Network
  • Energy Efficiency
  • Hardware Accelerator
  • Systolic Arrays
  • Timing Error
  • Timing Speculation

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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