Eliminating the timing penalty of scan

Ozgur Sinanoglu, Vishwani D. Agrawal

Research output: Contribution to journalArticle

Abstract

Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a pair of scan cell transformation techniques that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. The first technique is an ad-hoc technique, while the second one is the retiming technique applied on the scan logic. The proposed transformation techniques retain the test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan in a cost-effective way and thus enhancing the functional speed of integrated circuits.

Original languageEnglish (US)
Pages (from-to)103-114
Number of pages12
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume29
Issue number1
DOIs
StatePublished - Feb 25 2013

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Design for testability
Flip flop circuits
Integrated circuits
Energy dissipation
Degradation
Costs

Keywords

  • Multiplexer delay
  • Scan penalty
  • Scan retiming
  • Timing penalty

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Eliminating the timing penalty of scan. / Sinanoglu, Ozgur; Agrawal, Vishwani D.

In: Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 29, No. 1, 25.02.2013, p. 103-114.

Research output: Contribution to journalArticle

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