Eliminating performance penalty of scan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a scan cell transformation technique that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. By inserting a few shadow flip-flops properly, the proposed transformation technique retains test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan quickly and cost-effectively, and thus in enhancing functional speed of integrated circuits.

Original languageEnglish (US)
Title of host publicationProceedings - 25th International Conference on VLSI Design, VLSI Design 2012 - Held Jointly with 11th International Conference on Embedded Systems
PublisherIEEE Computer Society
Pages346-351
Number of pages6
ISBN (Print)9780769546384
DOIs
StatePublished - Jan 1 2012
Event25th International Conference on VLSI Design, VLSID 2012 and the 11th International Conference on Embedded Systems - Hyderabad, India
Duration: Jan 7 2012Jan 11 2012

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other25th International Conference on VLSI Design, VLSID 2012 and the 11th International Conference on Embedded Systems
CountryIndia
CityHyderabad
Period1/7/121/11/12

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Sinanoglu, O. (2012). Eliminating performance penalty of scan. In Proceedings - 25th International Conference on VLSI Design, VLSI Design 2012 - Held Jointly with 11th International Conference on Embedded Systems (pp. 346-351). [6167776] (Proceedings of the IEEE International Conference on VLSI Design). IEEE Computer Society. https://doi.org/10.1109/VLSID.2012.95