Electromigration reliability enhancement via bus activity distribution

Aurobindo Dasgupta, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Electromigration induced degradation in integrated circuits has been accelerated by continuous scaling of device dimensions. We present a methodology for synthesizing high-reliability and low-energy microarchitectures at the RT level by judiciously binding and scheduling the data transfers of a control data flow graph (CDFG) representation of the application onto the buses in the microarchitecture. The proposed method accounts for correlations between data transfers and the constraints on the number of buses, area and delay.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherIEEE
Pages353-356
Number of pages4
StatePublished - 1996
EventProceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA
Duration: Jun 3 1996Jun 7 1996

Other

OtherProceedings of the 1996 33rd Annual Design Automation Conference
CityLas Vegas, NV, USA
Period6/3/966/7/96

Fingerprint

Electromigration
Data transfer
Data flow graphs
Integrated circuits
Scheduling
Degradation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Dasgupta, A., & Karri, R. (1996). Electromigration reliability enhancement via bus activity distribution. In Proceedings - Design Automation Conference (pp. 353-356). IEEE.

Electromigration reliability enhancement via bus activity distribution. / Dasgupta, Aurobindo; Karri, Ramesh.

Proceedings - Design Automation Conference. IEEE, 1996. p. 353-356.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dasgupta, A & Karri, R 1996, Electromigration reliability enhancement via bus activity distribution. in Proceedings - Design Automation Conference. IEEE, pp. 353-356, Proceedings of the 1996 33rd Annual Design Automation Conference, Las Vegas, NV, USA, 6/3/96.
Dasgupta A, Karri R. Electromigration reliability enhancement via bus activity distribution. In Proceedings - Design Automation Conference. IEEE. 1996. p. 353-356
Dasgupta, Aurobindo ; Karri, Ramesh. / Electromigration reliability enhancement via bus activity distribution. Proceedings - Design Automation Conference. IEEE, 1996. pp. 353-356
@inproceedings{c4869d6e2b0f4ed2bf4fa0f26e5c45b1,
title = "Electromigration reliability enhancement via bus activity distribution",
abstract = "Electromigration induced degradation in integrated circuits has been accelerated by continuous scaling of device dimensions. We present a methodology for synthesizing high-reliability and low-energy microarchitectures at the RT level by judiciously binding and scheduling the data transfers of a control data flow graph (CDFG) representation of the application onto the buses in the microarchitecture. The proposed method accounts for correlations between data transfers and the constraints on the number of buses, area and delay.",
author = "Aurobindo Dasgupta and Ramesh Karri",
year = "1996",
language = "English (US)",
pages = "353--356",
booktitle = "Proceedings - Design Automation Conference",
publisher = "IEEE",

}

TY - GEN

T1 - Electromigration reliability enhancement via bus activity distribution

AU - Dasgupta, Aurobindo

AU - Karri, Ramesh

PY - 1996

Y1 - 1996

N2 - Electromigration induced degradation in integrated circuits has been accelerated by continuous scaling of device dimensions. We present a methodology for synthesizing high-reliability and low-energy microarchitectures at the RT level by judiciously binding and scheduling the data transfers of a control data flow graph (CDFG) representation of the application onto the buses in the microarchitecture. The proposed method accounts for correlations between data transfers and the constraints on the number of buses, area and delay.

AB - Electromigration induced degradation in integrated circuits has been accelerated by continuous scaling of device dimensions. We present a methodology for synthesizing high-reliability and low-energy microarchitectures at the RT level by judiciously binding and scheduling the data transfers of a control data flow graph (CDFG) representation of the application onto the buses in the microarchitecture. The proposed method accounts for correlations between data transfers and the constraints on the number of buses, area and delay.

UR - http://www.scopus.com/inward/record.url?scp=0029720341&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029720341&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029720341

SP - 353

EP - 356

BT - Proceedings - Design Automation Conference

PB - IEEE

ER -