Abstract
Processor-array architectures for the efficient implementation of the generalised predictive-control (GPC) algorithm are introduced, each exhibiting different area/time performance, processor utilisation and degree of programmability. The special features that the partial algorithms of GPC exhibit have been exploited, to derive efficient architectures of low complexity. A remarkable reduction of the execution time required for a complete cycle of the algorithm is achieved, compared with the long delay of executing the algorithm on a single processor.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 47-54 |
| Number of pages | 8 |
| Journal | IEE Proceedings: Control Theory and Applications |
| Volume | 145 |
| Issue number | 1 |
| DOIs | |
| State | Published - Jan 1 1998 |
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Keywords
- Predictive-control algorithms
- Processor-arrays
ASJC Scopus subject areas
- Control and Systems Engineering
- Instrumentation
- Electrical and Electronic Engineering
Cite this
Efficient processor arrays for the implementation of the generalised predictive-control algorithm. / Karagianni, K.; Chronopoulos, T.; Tzes, Antonios; Kousspulas, N.; Stouraitis, T.
In: IEE Proceedings: Control Theory and Applications, Vol. 145, No. 1, 01.01.1998, p. 47-54.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Efficient processor arrays for the implementation of the generalised predictive-control algorithm
AU - Karagianni, K.
AU - Chronopoulos, T.
AU - Tzes, Antonios
AU - Kousspulas, N.
AU - Stouraitis, T.
PY - 1998/1/1
Y1 - 1998/1/1
N2 - Processor-array architectures for the efficient implementation of the generalised predictive-control (GPC) algorithm are introduced, each exhibiting different area/time performance, processor utilisation and degree of programmability. The special features that the partial algorithms of GPC exhibit have been exploited, to derive efficient architectures of low complexity. A remarkable reduction of the execution time required for a complete cycle of the algorithm is achieved, compared with the long delay of executing the algorithm on a single processor.
AB - Processor-array architectures for the efficient implementation of the generalised predictive-control (GPC) algorithm are introduced, each exhibiting different area/time performance, processor utilisation and degree of programmability. The special features that the partial algorithms of GPC exhibit have been exploited, to derive efficient architectures of low complexity. A remarkable reduction of the execution time required for a complete cycle of the algorithm is achieved, compared with the long delay of executing the algorithm on a single processor.
KW - Predictive-control algorithms
KW - Processor-arrays
UR - http://www.scopus.com/inward/record.url?scp=0031651624&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0031651624&partnerID=8YFLogxK
U2 - 10.1049/ip-cta:19981637
DO - 10.1049/ip-cta:19981637
M3 - Article
AN - SCOPUS:0031651624
VL - 145
SP - 47
EP - 54
JO - IEE Proceedings: Control Theory and Applications
JF - IEE Proceedings: Control Theory and Applications
SN - 1350-2379
IS - 1
ER -