Efficient processor arrays for the implementation of the generalised predictive-control algorithm

K. Karagianni, T. Chronopoulos, A. Tzes, N. Kousspulas, T. Stouraitis

Research output: Contribution to journalArticle


Processor-array architectures for the efficient implementation of the generalised predictive-control (GPC) algorithm are introduced, each exhibiting different area/time performance, processor utilisation and degree of programmability. The special features that the partial algorithms of GPC exhibit have been exploited, to derive efficient architectures of low complexity. A remarkable reduction of the execution time required for a complete cycle of the algorithm is achieved, compared with the long delay of executing the algorithm on a single processor.

Original languageEnglish (US)
Pages (from-to)47-54
Number of pages8
JournalIEE Proceedings: Control Theory and Applications
Issue number1
StatePublished - Jan 1 1998



  • Predictive-control algorithms
  • Processor-arrays

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Instrumentation
  • Electrical and Electronic Engineering

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