Efficient processor arrays for the implementation of the generalised predictive-control algorithm

K. Karagianni, T. Chronopoulos, Antonios Tzes, N. Kousspulas, T. Stouraitis

    Research output: Contribution to journalArticle

    Abstract

    Processor-array architectures for the efficient implementation of the generalised predictive-control (GPC) algorithm are introduced, each exhibiting different area/time performance, processor utilisation and degree of programmability. The special features that the partial algorithms of GPC exhibit have been exploited, to derive efficient architectures of low complexity. A remarkable reduction of the execution time required for a complete cycle of the algorithm is achieved, compared with the long delay of executing the algorithm on a single processor.

    Original languageEnglish (US)
    Pages (from-to)47-54
    Number of pages8
    JournalIEE Proceedings: Control Theory and Applications
    Volume145
    Issue number1
    DOIs
    StatePublished - Jan 1 1998

    Fingerprint

    Parallel processing systems
    central processing units
    cycles

    Keywords

    • Predictive-control algorithms
    • Processor-arrays

    ASJC Scopus subject areas

    • Control and Systems Engineering
    • Instrumentation
    • Electrical and Electronic Engineering

    Cite this

    Efficient processor arrays for the implementation of the generalised predictive-control algorithm. / Karagianni, K.; Chronopoulos, T.; Tzes, Antonios; Kousspulas, N.; Stouraitis, T.

    In: IEE Proceedings: Control Theory and Applications, Vol. 145, No. 1, 01.01.1998, p. 47-54.

    Research output: Contribution to journalArticle

    Karagianni, K. ; Chronopoulos, T. ; Tzes, Antonios ; Kousspulas, N. ; Stouraitis, T. / Efficient processor arrays for the implementation of the generalised predictive-control algorithm. In: IEE Proceedings: Control Theory and Applications. 1998 ; Vol. 145, No. 1. pp. 47-54.
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