Efficient buffering and scheduling for a single-chip crosspoint-queued switch

Zizhong Cao, Shivendra Panwar

Research output: Contribution to journalArticle

Abstract

The single-chip crosspoint-queued (CQ) switch is a compact switching architecture that has all its buffers placed at the crosspoints of input and output lines. Scheduling is also performed inside the switching core and does not rely on latency-limited communications with input or output line-cards. Compared with other legacy switching architectures, the CQ switch has the advantages of high throughput, minimal delay, low scheduling complexity, and no speedup requirement. However, the crosspoint buffers are small and segregated; thus, how to efficiently use the buffers and avoid packet drops remains a major problem that needs to be addressed. In this paper, we consider load balancing, deflection routing, and buffer pooling for efficient buffer sharing in the CQ switch. We also design scheduling algorithms to maintain the correct packet order even while employing multi-path switching and resolve contentions caused by multiplexing. All these techniques require modest hardware modifications and memory speedup in the switching core but can greatly boost the buffer utilizations by up to 10 times and reduce the packet drop rates by one to three orders of magnitude. Extensive simulations and analyses have been done to demonstrate the advantages of the proposed buffering and scheduling techniques. By pushing the on-chip memory to the limit of current ASIC technology, we show that a cell drop rate of 10-8, which is low enough for practical uses, can be achieved under real Internet traffic traces corresponding to a load of 0.9.

Original languageEnglish (US)
Article number6802344
Pages (from-to)2034-2050
Number of pages17
JournalIEEE Transactions on Communications
Volume62
Issue number6
DOIs
StatePublished - 2014

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Scheduling
Switches
Data storage equipment
Application specific integrated circuits
Scheduling algorithms
Multiplexing
Computer hardware
Resource allocation
Throughput
Internet
Communication

Keywords

  • Buffer pooling
  • Crossbar
  • Deflection routing
  • Load balancing
  • Scheduling
  • Single-chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Efficient buffering and scheduling for a single-chip crosspoint-queued switch. / Cao, Zizhong; Panwar, Shivendra.

In: IEEE Transactions on Communications, Vol. 62, No. 6, 6802344, 2014, p. 2034-2050.

Research output: Contribution to journalArticle

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