Dynamic scan chain partitioning for reducing peak shift power during test

Sobeeh Almukhaizim, Ozgur Sinanoglu

    Research output: Contribution to journalArticle

    Abstract

    Scan chain partitioning techniques are quite effective in reducing test power, as the rippling in the clock network, scan chains, and logic is reduced altogether. Partitioning approaches implemented in a static manner may fail to reduce peak power down to the desired level, however, depending on the transition distribution of the problematic pattern in the statically constructed scan chain partitions. In this paper, we propose a dynamic partitioning approach capable of adapting to the transition distribution of any test pattern and, thus, of delivering near-perfect peak power reductions. The proposed dynamic partitioning hardware allows for the partitioning reconfiguration on a per test pattern basis, hence delivering a solution that is test set independent, yet its quality is superior to that of any test set dependent solution.

    Original languageEnglish (US)
    Article number4757340
    Pages (from-to)298-302
    Number of pages5
    JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Volume28
    Issue number2
    DOIs
    StatePublished - Feb 1 2009

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    Keywords

    • Dynamic partitioning
    • Scan chain partitioning
    • Test power reduction

    ASJC Scopus subject areas

    • Software
    • Computer Graphics and Computer-Aided Design
    • Electrical and Electronic Engineering

    Cite this

    Dynamic scan chain partitioning for reducing peak shift power during test. / Almukhaizim, Sobeeh; Sinanoglu, Ozgur.

    In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 2, 4757340, 01.02.2009, p. 298-302.

    Research output: Contribution to journalArticle

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