DfT support for launch and capture power reduction in launch-off-capture testing

Samah Mohamed Saeed, Ozgur Sinanoglu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    At-speed or even faster-than-at-speed testing of VLSI circuits aim at a high quality screening of VLSI circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable to lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose DfT support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner. The DfT support we outline in this paper enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design flow compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering launch/capture power.

    Original languageEnglish (US)
    Title of host publicationProceedings - 2012 17th IEEE European Test Symposium, ETS 2012
    DOIs
    StatePublished - Aug 13 2012
    Event2012 17th IEEE European Test Symposium, ETS 2012 - Annecy, France
    Duration: May 28 2012Jun 1 2012

    Other

    Other2012 17th IEEE European Test Symposium, ETS 2012
    CountryFrance
    CityAnnecy
    Period5/28/126/1/12

    Fingerprint

    VLSI circuits
    Testing
    Costs
    Screening

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Saeed, S. M., & Sinanoglu, O. (2012). DfT support for launch and capture power reduction in launch-off-capture testing. In Proceedings - 2012 17th IEEE European Test Symposium, ETS 2012 [6233001] https://doi.org/10.1109/ETS.2012.6233001

    DfT support for launch and capture power reduction in launch-off-capture testing. / Saeed, Samah Mohamed; Sinanoglu, Ozgur.

    Proceedings - 2012 17th IEEE European Test Symposium, ETS 2012. 2012. 6233001.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Saeed, SM & Sinanoglu, O 2012, DfT support for launch and capture power reduction in launch-off-capture testing. in Proceedings - 2012 17th IEEE European Test Symposium, ETS 2012., 6233001, 2012 17th IEEE European Test Symposium, ETS 2012, Annecy, France, 5/28/12. https://doi.org/10.1109/ETS.2012.6233001
    Saeed SM, Sinanoglu O. DfT support for launch and capture power reduction in launch-off-capture testing. In Proceedings - 2012 17th IEEE European Test Symposium, ETS 2012. 2012. 6233001 https://doi.org/10.1109/ETS.2012.6233001
    Saeed, Samah Mohamed ; Sinanoglu, Ozgur. / DfT support for launch and capture power reduction in launch-off-capture testing. Proceedings - 2012 17th IEEE European Test Symposium, ETS 2012. 2012.
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