Design-space exploration of power-aware on/off interconnection networks

Research output: Contribution to journalConference article

Abstract

With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems. As communication links consume significant power regardless of utilization, we propose and investigate power-aware networks whose links are turned on and off in response to bursts and dips in traffic. We explore the design space of such on/off networks, outlining a 5-step design methodology along with solutions at each step that can form the building blocks of numerous designs. Two specific designs targeting links with substantially different on/off times are then presented and evaluated. Our simulations show that up to 54.4% power savings can be achieved along with at most 7.5% increase in latency.

Original languageEnglish (US)
Pages (from-to)510-517
Number of pages8
JournalProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Publication statusPublished - Dec 1 2004
EventProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States
Duration: Oct 11 2004Oct 13 2004

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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