Design of packet-fair queuing schedulers using a RAM-based searching engine

H. Jonathan Chao, Yau Ren Jenq, Xiaolei Guo, Cheuk H. Lam

Research output: Contribution to journalArticle

Abstract

The implementation of packet-fair queuing (PFQ) schedulers, which aim at approximating the generalized processor sharing (GPS) policy, is a central issue for providing multimedia services with various quality-of-service (QoS) requirements in packet-switching networks. In the PFQ scheduler, packets are usually time stamped with a value based on some algorithm and are transmitted with an increasing order of the time-stamp values. One of the most challenging issues is to search for the smallest time-stamp value among hundreds of thousands of sessions. In this paper, we propose a novel RAM-based searching engine (RSE) to speed up the searching process by using the concept of hierarchical searching with a tree data structure. The time for searching the smallest time stamp is independent of the number of sessions in the system and is only bounded by the memory accesses needed. The RSE can be implemented with commercial memory and field programmable gate array (FPGA) chips in a cost-effective manner. With the extension of the RSE, we propose a two-dimensional (2-D) RSE architecture to implement a general shaper-scheduler. Other challenging issues, such as time-stamp overflow and aging, are also addressed in the paper.

Original languageEnglish (US)
Pages (from-to)1105-1126
Number of pages22
JournalIEEE Journal on Selected Areas in Communications
Volume17
Issue number6
DOIs
StatePublished - Jun 1999

Fingerprint

Random access storage
Engines
Data storage equipment
Packet switching
Multimedia services
Packet networks
Switching networks
Data structures
Field programmable gate arrays (FPGA)
Quality of service
Aging of materials
Costs

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Design of packet-fair queuing schedulers using a RAM-based searching engine. / Chao, H. Jonathan; Jenq, Yau Ren; Guo, Xiaolei; Lam, Cheuk H.

In: IEEE Journal on Selected Areas in Communications, Vol. 17, No. 6, 06.1999, p. 1105-1126.

Research output: Contribution to journalArticle

Chao, H. Jonathan ; Jenq, Yau Ren ; Guo, Xiaolei ; Lam, Cheuk H. / Design of packet-fair queuing schedulers using a RAM-based searching engine. In: IEEE Journal on Selected Areas in Communications. 1999 ; Vol. 17, No. 6. pp. 1105-1126.
@article{c5d13719a7014648911d828ba8232f20,
title = "Design of packet-fair queuing schedulers using a RAM-based searching engine",
abstract = "The implementation of packet-fair queuing (PFQ) schedulers, which aim at approximating the generalized processor sharing (GPS) policy, is a central issue for providing multimedia services with various quality-of-service (QoS) requirements in packet-switching networks. In the PFQ scheduler, packets are usually time stamped with a value based on some algorithm and are transmitted with an increasing order of the time-stamp values. One of the most challenging issues is to search for the smallest time-stamp value among hundreds of thousands of sessions. In this paper, we propose a novel RAM-based searching engine (RSE) to speed up the searching process by using the concept of hierarchical searching with a tree data structure. The time for searching the smallest time stamp is independent of the number of sessions in the system and is only bounded by the memory accesses needed. The RSE can be implemented with commercial memory and field programmable gate array (FPGA) chips in a cost-effective manner. With the extension of the RSE, we propose a two-dimensional (2-D) RSE architecture to implement a general shaper-scheduler. Other challenging issues, such as time-stamp overflow and aging, are also addressed in the paper.",
author = "Chao, {H. Jonathan} and Jenq, {Yau Ren} and Xiaolei Guo and Lam, {Cheuk H.}",
year = "1999",
month = "6",
doi = "10.1109/49.772442",
language = "English (US)",
volume = "17",
pages = "1105--1126",
journal = "IEEE Journal on Selected Areas in Communications",
issn = "0733-8716",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",

}

TY - JOUR

T1 - Design of packet-fair queuing schedulers using a RAM-based searching engine

AU - Chao, H. Jonathan

AU - Jenq, Yau Ren

AU - Guo, Xiaolei

AU - Lam, Cheuk H.

PY - 1999/6

Y1 - 1999/6

N2 - The implementation of packet-fair queuing (PFQ) schedulers, which aim at approximating the generalized processor sharing (GPS) policy, is a central issue for providing multimedia services with various quality-of-service (QoS) requirements in packet-switching networks. In the PFQ scheduler, packets are usually time stamped with a value based on some algorithm and are transmitted with an increasing order of the time-stamp values. One of the most challenging issues is to search for the smallest time-stamp value among hundreds of thousands of sessions. In this paper, we propose a novel RAM-based searching engine (RSE) to speed up the searching process by using the concept of hierarchical searching with a tree data structure. The time for searching the smallest time stamp is independent of the number of sessions in the system and is only bounded by the memory accesses needed. The RSE can be implemented with commercial memory and field programmable gate array (FPGA) chips in a cost-effective manner. With the extension of the RSE, we propose a two-dimensional (2-D) RSE architecture to implement a general shaper-scheduler. Other challenging issues, such as time-stamp overflow and aging, are also addressed in the paper.

AB - The implementation of packet-fair queuing (PFQ) schedulers, which aim at approximating the generalized processor sharing (GPS) policy, is a central issue for providing multimedia services with various quality-of-service (QoS) requirements in packet-switching networks. In the PFQ scheduler, packets are usually time stamped with a value based on some algorithm and are transmitted with an increasing order of the time-stamp values. One of the most challenging issues is to search for the smallest time-stamp value among hundreds of thousands of sessions. In this paper, we propose a novel RAM-based searching engine (RSE) to speed up the searching process by using the concept of hierarchical searching with a tree data structure. The time for searching the smallest time stamp is independent of the number of sessions in the system and is only bounded by the memory accesses needed. The RSE can be implemented with commercial memory and field programmable gate array (FPGA) chips in a cost-effective manner. With the extension of the RSE, we propose a two-dimensional (2-D) RSE architecture to implement a general shaper-scheduler. Other challenging issues, such as time-stamp overflow and aging, are also addressed in the paper.

UR - http://www.scopus.com/inward/record.url?scp=0032666934&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032666934&partnerID=8YFLogxK

U2 - 10.1109/49.772442

DO - 10.1109/49.772442

M3 - Article

VL - 17

SP - 1105

EP - 1126

JO - IEEE Journal on Selected Areas in Communications

JF - IEEE Journal on Selected Areas in Communications

SN - 0733-8716

IS - 6

ER -