Design of high-radix Clos Network-on-Chip

Yu Hsiang Kao, Najla Alfaraj, Ming Yang, H. Jonathan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Many high-radix Network-on-Chip (NOC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe Clos Network-on-Chip (CNOC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose (1) a high-radix router architecture with Virtual Output Queue (VOQ) buffer structure and Packet Mode Dual Round-Robin Matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in CNOC, (2) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. Experimental results show that the throughput of a 64-node 3-stage CNOC under uniform traffic increases from 62% to 78% by replacing the baseline routers with PDRRM VOQ routers. We also compared CNOC with other NOC topologies, and found that using the new design techniques, CNOC has the highest throughput, lowest zero-load latency, and best power efficiency.

Original languageEnglish (US)
Title of host publicationNOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip
Pages181-188
Number of pages8
DOIs
StatePublished - 2010
Event4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010 - Grenoble, France
Duration: May 3 2010May 6 2010

Other

Other4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010
CountryFrance
CityGrenoble
Period5/3/105/6/10

Fingerprint

Routers
Throughput
Topology
Network performance
Network-on-chip
Scheduling algorithms
Resource allocation
Electric power utilization
Wire
Planning
Processing

Keywords

  • Chip multiprocessor
  • Clos network
  • High radix NOC
  • Network on Chip

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kao, Y. H., Alfaraj, N., Yang, M., & Chao, H. J. (2010). Design of high-radix Clos Network-on-Chip. In NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip (pp. 181-188). [5507549] https://doi.org/10.1109/NOCS.2010.27

Design of high-radix Clos Network-on-Chip. / Kao, Yu Hsiang; Alfaraj, Najla; Yang, Ming; Chao, H. Jonathan.

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. 2010. p. 181-188 5507549.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kao, YH, Alfaraj, N, Yang, M & Chao, HJ 2010, Design of high-radix Clos Network-on-Chip. in NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip., 5507549, pp. 181-188, 4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010, Grenoble, France, 5/3/10. https://doi.org/10.1109/NOCS.2010.27
Kao YH, Alfaraj N, Yang M, Chao HJ. Design of high-radix Clos Network-on-Chip. In NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. 2010. p. 181-188. 5507549 https://doi.org/10.1109/NOCS.2010.27
Kao, Yu Hsiang ; Alfaraj, Najla ; Yang, Ming ; Chao, H. Jonathan. / Design of high-radix Clos Network-on-Chip. NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. 2010. pp. 181-188
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